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Verification IP Hastens the Design of CXL 3.0

Verification IP Hastens the Design of CXL 3.0
by Dave Bursky on 09-21-2022 at 6:00 am

cxl standards 1

Although version 2.0 of the Computer Express Link (CXL) standard is just making it into new designs, the next generation, version 3.0, has been approved and is now ready for designers to implement the new silicon and firmware needed to meet the new standard’s performance specifications. CXL, an open industry-standard interconnect,… Read More


Verifying Inter-Chiplet Communication

Verifying Inter-Chiplet Communication
by Daniel Nenni on 07-04-2022 at 6:00 am

UCIe min

Chiplets are hot now as a way to extend Moore’s Law, dividing functionality across multiple die within a single package. It’s no longer practical to jam all functionality onto a single die in the very latest processes, exceeding reticle limits in some cases and in others straining cost/yield. This is not an academic concern. Already… Read More


Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express

Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express
by Daniel Payne on 03-29-2022 at 10:00 am

Fungible min

Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking… Read More


PCIe 6.0, LPDDR5, HBM2E and HBM3 Speed Adapters to FPGA Prototyping Solutions

PCIe 6.0, LPDDR5, HBM2E and HBM3 Speed Adapters to FPGA Prototyping Solutions
by Kalar Rajendiran on 12-15-2021 at 6:00 am

Avery PCIe Speed Adapter IP at Work

We live in the age of big data. No matter how fast and complex modern SoCs are, it all comes down to how quickly data can get in and out that determines the system performance. And, there is a lot of data that today’s systems need to process. Naturally, system interfaces such as PCIe, DDR, HBM, etc., have been evolving rapidly too, to support… Read More


Controlling the Automotive Network – CAN and TSN Update

Controlling the Automotive Network – CAN and TSN Update
by Bernard Murphy on 08-18-2021 at 6:00 am

automotive networks

Cars are hotbeds of systems innovation. I’ve been fortunate to be asked to write about many of these areas, from the MEMS underlying sensors to ISPs and radars, intelligent imaging and sensor fusion. And many aspects of design for safety within the SoCs around a car. But I haven’t written much about the networks connecting these … Read More


Webinar: Learn about NVMe conformance Testing

Webinar: Learn about NVMe conformance Testing
by Daniel Payne on 06-29-2021 at 6:00 am

QEMU min

Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in … Read More


Avery Levels Up, Starting with CXL

Avery Levels Up, Starting with CXL
by Bernard Murphy on 05-25-2021 at 6:00 am

QEMU block diagram min

Let me acknowledge up front that Avery isn’t the most visible EDA company around. If you know of them, you probably know their X-propagation simulator. Widely respected and used, satisfying a specialized need. They have also been quietly building over the years a stable of VIPs and happy customers, with a special focus on VIPs for… Read More