Domain specific processors are a mega-trend in the semiconductor industry, so we see new three letter acronyms like DPU, for Data Processing Unit. System level performance can actually be improved by moving some of the tasks away from the CPU. Companies like Xilinx (Alveo), Amazon (Nitro) and NVIDIA (BlueField) have been talking about DPU architecture for awhile now, and the SmartNIC is now being called a DPU in the hyper-scale data centers.
Last month I read about a new company, Fungible, as they announced their own DPU, and for verification of the PCI Express they used VIP from Avery Design Systems. Fungible presented their F1 DPU architecture at the Hot Chips conference, and here’s the block diagram where PCIe is on one side, and Ethernet on the other:
To learn more about DPU and PCI Express VIP I scheduled a Zoom call with Chakravarthy Kosaraju, SVP, Silicon Design and Validation at Fungible, and Christopher Browy, VP of Sales/Marketing at Avery Design Systems. In the big picture of things the CPU used to be powerful enough to handle all networking tasks, but now with so much data traffic it simply overwhelms the CPU cycles, so both the SmartNIC and DPU approaches are growing in popularity to get around CPU bottlenecks.
Disaggregation is the big trend in the data center now, because it allows more efficient use of resources like storage and data. CPUs paired with GPUs are trying to coordinate all the other PUs. The PCIe slot handles data between the server and storage. The Fungible F1 DPU goes into a storage server, manages all of the SSDs, and even handles cryptography.
Avery Design Systems and Fungible have been working together for the past 3-4 year on PCIe VIP. On the VIP side the engineering team at Avery have now developed support for over 60 protocols, where PCIe is just one of their high speed IO protocols. The PCIe standard started way back in 2003, created by Intel, Dell, HP and IBM; now the specifications are managed by the PCI-SIG, a group of 900 companies.
When using PCIe in a SoC, you really don’t want to re-invent the wheel by hand-coding your own VIP, because it takes too many man-years of effort to do so, and Avery has been involved with the PCIe standard since version 1.0, and now we’re up to version 6.0 of the spec. Avery is a member of the PCI-SIG, and has many customers using their PCIe VIP, so that provided the team at Fungible the confidence to choose Avery for the version 5.0 VIP.
The team of globally dispersed verification engineers at Fungible were able to readily contact Avery with support questions about their new VIP. Fungible used VIP from Avery, among others, for its F1 DPU project. Complimentary feedback was provided by Fungible regarding the helpfulness of the VIP output files for debugging, the usefulness of the tracker files, appreciation for the extensive protocol checks, the speed of switch enumeration they experienced, and the ability to verify a system topology with ease. The F1 chips came back working successfully on first silicon; proving VIP improved their success rate. There are over 100 customers using the PCIe VIP from Avery, which speaks volumes about its stability and value.
The VIP from Avery is sold as time-based licensing, and has a flexible spending model (monthly remixing). Every simulation checks out both a simulator and VIP license for users.
The latest PCIe version is 6.0 right now, and there have been two updates already, even before full approval by the PCI-SIG. Typically Avery will do a quarterly update for VIP, tracking the standards so that all features are implemented. They have thousands of test cases and protocol checks, plus bug fixes and patches are part of their normal procedure.
Fungible was able to get first silicon success using a methodology of IP and VIP re-use on their F1 DPU chip, aimed at the datacenter market. Choosing Avery Design Systems as a partner for PCIe VIP was part of a multi-year relationship between the companies, and I expect them to continue that into the future.
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