WP_Term Object
(
    [term_id] => 17274
    [name] => Avery Design Systems
    [slug] => avery-design-systems
    [term_group] => 0
    [term_taxonomy_id] => 17274
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 7
    [filter] => raw
    [cat_ID] => 17274
    [category_count] => 7
    [category_description] => 
    [cat_name] => Avery Design Systems
    [category_nicename] => avery-design-systems
    [category_parent] => 178
)
            
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WP_Term Object
(
    [term_id] => 17274
    [name] => Avery Design Systems
    [slug] => avery-design-systems
    [term_group] => 0
    [term_taxonomy_id] => 17274
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 7
    [filter] => raw
    [cat_ID] => 17274
    [category_count] => 7
    [category_description] => 
    [cat_name] => Avery Design Systems
    [category_nicename] => avery-design-systems
    [category_parent] => 178
)

Webinar: Learn about NVMe conformance Testing

Webinar: Learn about NVMe conformance Testing
by Daniel Payne on 06-29-2021 at 6:00 am

Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in using SSD was at a web hosting vendor, and the new, quicker page loading times meant that I was never going back to the slow, older HDD technology.

Of course, to make our electronics industry really scale requires cooperation along with standards, and for SSD memory we look to NVM Express group, the non-profit consortium, where they have specified exactly how host software should talk with NVM using different transports, like:

  • PCI Express
  • RDMA
  • TCP

Moving from the NVMe 1.4b standard to version 2.0 adds new features, so engineers involved in designing, verifying and validating SSD systems need to keep updated. You should consider attending a webinar on July 14th, where experts from the University of New Hampshire InterOperability Laboratory (UNH-IOL) team up with Avery Design Systems to talk about conformance testing.

Webinar Agenda

Daniel Nenni from SemiWiki will provide an industry overview, and then David Woolf from UNH-IOL and Luis Rodriguez from Avery Design Solutions will provide insight about:

  • NVMe 1.4 and 2.0 standards, what’s changed
  • OCP NVMe features
  • Faster testing and validation with UNH-IOL and Avery together
  • IOL INTERACT overview and plugfest, demo on QEMU-NVMe
  • Using pre-silicon RTL simulation and running engineering regressions
  • The QEMU virtual host and SoC system co-simulation from Avery

Speaking with David Woolf I learned that NVMe can be used in mobile devices, laptops, desktops and even on servers in the data center, so quite a wide span of use cases, all that need to be tested for compliance. Instead of waiting to run compliance tests at the end of a NVM project, there’s a way to run compliance testing while your project is still in the design phase, using emulation, when it’s much easier to make changes. This is a great example of Shift-left thinking, to move testing much earlier during the product lifecycle.

NVMe Environment

Here’s a diagram of using QEMU to emulate NVMe conformance testing:

QEMU min

By co-simulating the SoC RTL code with the QEMU open software virtual machine, a software engineer can then develop and build their firmware, drivers and even applications to run on a Linux or Windows platform. Issues with software can be debugged with GDB or KGDB, while using the cycle accurate SystemVerilog RTL for the SoC.

Summary

Standards make the world go round, and the new NVMe 2.0 standard is ready to use for systems companies working on SSD-based electronics. Doing your conformance checking early in the design process is going to save you time and the surprise of waiting until production, when it’s too late to make design changes. Avery Design Systems has verification IP well suited to shift-left the conformance testing, along with IO INTERACT from UNH IOL.

Enjoy the webinar on July 14, 2021, starting at 1PM Eastern, 10AM Pacific time. Register online here.

Also Read:

Avery Levels Up, Starting with CXL

Data Processing Unit (DPU) uses Verification IP (VIP) for PCI Express

PCIe 6.0, LPDDR5, HBM2E and HBM3 Speed Adapters to FPGA Prototyping Solutions

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