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June 8, 2018

When FPGA Design Looks More Like ASIC Design

When FPGA Design Looks More Like ASIC Design
by Bernard Murphy on 06-08-2018 at 7:00 am
Categories: EDA, FPGA, Synopsys

I am sure there are many FPGA designers who are quite content to rely on hardware vendor tools to define, check, implement and burn their FPGAs, and who prefer to test in-system to validate functionality. But that approach is unlikely to work when you’re building on the big SoC platforms – Zynq, Arria and even the big non-SoC devices.… Read More

January 25, 2018

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am
Categories: ARM, EDA, Synopsys

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register… Read More

February 3, 2017June 14, 2019

Verifying Design for In-Car Networks

Verifying Design for In-Car Networks
by Bernard Murphy on 02-03-2017 at 7:00 am
Categories: Automotive, EDA, Synopsys

Once upon a time the role of electricity in a car was pretty modest: spark plugs, alternator, lighting, some simple instrumentation and maybe heating, all supported by an equally simple wiring harness (my wife has a 1962 Morris Minor, so I know exactly what the whole wiring harness looks like). How times have changed. Now most or … Read More

October 6, 2015

Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am
Categories: EDA, IP, Semiconductor Services

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More

September 29, 2015

Indian Railways and SoCs

Indian Railways and SoCs
by Sivakumar P R on 09-29-2015 at 4:00 pm
Categories: EDA

Last week I woke up late as usual and decided to flip through the news paper on Coffee to enjoy the lazy Sunday morning, but I ended up reading a sad news about a train accident. Everyday virtually we hear about minimum one accident. Indian Railways, wow, what a reliable transportation system we have built. It clearly indicates we have… Read More

August 26, 2015June 14, 2019

Secret Sauce of SmartDV and its CEO’s Vision

Secret Sauce of SmartDV and its CEO’s Vision
by Pawan Fangaria on 08-26-2015 at 4:00 pm
Categories: IP, SmartDV

SmartDV started as a small setup in Bangalore in 2008 and by now is one of the most respectable VIP (Verification IP) companies in the world. Having a portfolio of 83 VIPs in its kitty and growing, it has a large customer base, including the top semiconductor companies around the world. The company has grown significantly and is raring… Read More

July 2, 2015June 14, 2019

SmartDV at DAC and More

SmartDV at DAC and More
by Pawan Fangaria on 07-02-2015 at 7:00 am
Categories: IP, SmartDV

As we are aware about SmartDV Technologies, a fast emerging company in IP space with offices in Bangalore and San Diego, its booth in 52[SUP]nd[/SUP] DACwas located at a prominent position in front of DAC Pavilion on the exhibits floor. So, most of the crowd coming to attend sessions in DAC Pavilion had a glimpse of SmartDV. I met Deepak… Read More

June 8, 2015June 14, 2019

Next Generation Formal Technology to Boost Verification

Next Generation Formal Technology to Boost Verification
by Pawan Fangaria on 06-08-2015 at 12:00 pm
Categories: Cadence, EDA

With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More

April 17, 2015June 14, 2019

Successful Venture of an Indian Global VIP Company

Successful Venture of an Indian Global VIP Company
by Pawan Fangaria on 04-17-2015 at 10:00 am
Categories: IP, SmartDV

It’s rare that we find a truly Indian-based company operating globally in the semiconductor space. Although the ‘gold rush’ towards IP development in the last decade initiated many IP start-ups in India, today we rarely find Indian IP company names which are shining in the global arena. The story of services companies is different,… Read More

December 22, 2014June 14, 2019

Last VIP News of 2014

Last VIP News of 2014
by Eric Esteve on 12-22-2014 at 11:00 am
Categories: IP, Synopsys

It’s likely that most of the current Semiwiki readers didn’t read this article posted in 2011, comparing Cadence and Synopsys with the Soviet Union and the USA, sharing the world in 1944 during the Yalta Conference. I was explaining in my post that Synopsys’s strong influence was on Design IP when Cadence’s preferred domain was … Read More

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Tag: vip

When FPGA Design Looks More Like ASIC Design

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Verifying Design for In-Car Networks

Nine Cost Considerations to Keep IP Relevant –Part2

Indian Railways and SoCs

Secret Sauce of SmartDV and its CEO’s Vision

SmartDV at DAC and More

Next Generation Formal Technology to Boost Verification

Successful Venture of an Indian Global VIP Company

Last VIP News of 2014

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