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New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development

New Cadence Joint Enterprise Data and AI Platform Dramatically Accelerates AI-Driven Chip Design Development
by Kalar Rajendiran on 10-24-2022 at 10:00 am

Without data, there is no computing field to talk about, no technology world to awe at and not much of a semiconductor industry to work in. There is no argument that data is the foundational piece for everything, has been to date and will continue to be. While processing an application’s input data is essential to serve the intended purpose, a lot of collateral data is typically generated in the process of creating the desired output. Chip development projects are high on the list when it comes to the amount of collateral data generated. Analyzing collateral data could provide insights to enhance future products, yet it is not frequently done.

Things are changing. The availability of compute-related resources has grown tremendously over the years. Advancements in artificial intelligence (AI) and machine learning (ML)-based technologies have made intelligent analysis software possible. Over the last couple of years, Cadence has released many AI-driven software products to dramatically benefit the chip development efforts. And recently, Cadence announced its Joint Enterprise Data and AI (JedAI) Platform that unifies data sets across all Cadence computational software. The Cadence JedAI Platform is a big data analytics infrastructure that dramatically improves productivity and power, performance and area (PPA) by enabling AI-driven applications.

Three Major Aspects of Product Development

Before discussing the salient aspects of the JedAI platform, it’s worthwhile to summarize the AI-driven Cadence products that have already been in use for some time now.

Design

Last year, the company announced the Cadence Cerebrus™ Intelligent Chip Explorer, an AI-driven, automated RTL-to-GDS full-flow optimization tool. It takes PPA targets for a design or a block within a design. The user can provide a start and end point of the flow or tell the tool to do the full flow. It can run hundreds of different experiments very quickly and search a much larger space than is possible via manual means. Through ML techniques, Cerebrus helps increase EDA flow efficiencies and enables implementation tools to quickly converge on better placement and route and timing closure.

Optimization

Announced earlier this year was Optimality™ Intelligent System Explorer, Cadence’s system optimization platform. The platform delivers for system design what the Cerebrus platform delivers for chip design. The tool quickly and efficiently explores the design space to produce optimal electrical design performance. It helps optimize the system design by applying AI techniques to the results of multi-physics analyses.

Verification

Cadence recently announced the Verisium™ Artificial Intelligence (AI)-Driven Verification Platform. Verification and debug are major aspects of all chip development projects and rely on experience and creativity to execute. The Verisium platform is built on the JedAI Platform and is natively integrated with Cadence verification engines. It is a multi-run, multi-engine tool that applies AI models and ML techniques to perform root cause analysis for debug, optimize verification workloads and increase coverage.

Cadence JedAI Platform

Whether it is the design, verification or optimization efforts, a tremendous amount of data is generated. The data can be broadly categorized into design data, workflow data and workload data. For example, design RTL, netlist, physical layout shapes, timing analysis reports, etc., would fall into the design data category. The workflow data category would contain information about the specific tools and methodology used in the design process. And workload data refers to data about runtime, memory and storage usage and job inputs and inter-dependencies.

The JedAI Platform applies AI algorithms on the above types of data to optimize multiple runs of multiple engines across an entire SoC design and verification flow. It also analyzes historical workload data to predict resource requirements and schedule jobs for increased server farm utilization for both on-prem and on-cloud scenarios. The Platform allows engineering teams to visualize and uncover data trends and automatically generate strategies for improved design performance and engineering productivity.

1 Cadence Joint Enterprise Data and AI JedAI Platform

Benefits of Cadence JedAI Platform

By themselves, the earlier mentioned AI-driven design, verification and optimization platforms enable enhanced productivity and PPA benefits compared to traditional approaches. Even higher levels of benefits can be derived if data from these different platforms can be cross-leveraged. The JedAI Platform makes that possible by offering a common infrastructure for inter-communications. Built on top of this common infrastructure, data connectors allow for bi-directional transfer from a wide variety of Cadence tools and data sources. Also provided are general-purpose open data connectors for designers to easily import third-party data as needed. Support of open industry-standard user interfaces such as Python, Jupyter Notebook and REST APIs enable designers to create custom analytics applications as needed.

2 Cadence JedAI Platform Architecture

One of Many Use Cases

Various RTL modules of an SoC connect to different parts of an SoC using input and output ports. Understanding the timing criticality between the various modules is key to achieving the PPA goals of the SoC. A static timing analysis report does not make it easy or quick to gain these insights. But, with the module timing visualization and trend analysis app that is included with the JedAI Platform, customers can generate a module-based timing criticality report. The data visualization and analytics features of the JedAI Platform highlight the modules that communicate and the associated ports timings.

As the JedAI Platform can store many revisions of the SoC design data, it is possible to see how the RTL port timing changes based on different revisions of the source RTL. Equipped with this insight, RTL designers can make effective changes for improving timing within and across module boundaries. The changes are then communicated to the SoC implementation platform using the Innovus™ Implementation System’s data connector.

5 Module Timing Visualization and Trend Analysis App

Summary

With the Cadence JedAI Platform, Cadence has unified its computational software innovations in data and AI across its Verisium verification platform, its Cerebrus implementation platform, and its Optimality system optimization platform. The revolutionary JedAI Platform enables customers to meet increasingly stringent PPA, productivity and time-to-market demands of their respective market segments.

The Cadence JedAI press announcement can be found here and more details can be accessed in the product section of Cadence website.

Also Read:

Test Ordering for Agile. Innovation in Verification

Finally, A Serious Attack on Debug Productivity

Hazard Detection Using Petri Nets. Innovation in Verification

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