A Fresh Idea in Differential Energy Analysis

A Fresh Idea in Differential Energy Analysis
by Bernard Murphy on 09-06-2018 at 7:00 am

When I posted earlier on Qualcomm presenting with ANSYS on differential energy analysis, I assumed this was just the usual story on RTL power estimation being more accurate for relative estimation between different implementations. I sold them short. This turned out to be a much more interesting methodology for optimizing total… Read More


The Ising on the Cake

The Ising on the Cake
by Bernard Murphy on 10-27-2016 at 7:00 am

Just when you thought you knew all the possible foundations for computing, along comes another one. Forget Image Removedvon Neumann, this approach models Ising machines, systems built on solving a statistical ensemble model of ferromagnetism. The concept is quite simple. Imagine a lattice of magnetic dipoles/spins, each … Read More


There is more than C to worry about

There is more than C to worry about
by Don Dingee on 10-17-2016 at 4:00 pm

We periodically see that “software ate the world” line – I’m pretty sure I’ve used it a couple times myself. The fact is, software doesn’t run itself; never has, never will. Somewhere there has to be an underlying computer. First it was on beads, then in gears, then in tubes.… Read More


Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More


Semi execs look at IoT tradeoffs a bit differently

Semi execs look at IoT tradeoffs a bit differently
by Don Dingee on 08-15-2016 at 4:00 pm

What happens when you get a panel of four executives together with an industry-leading journalist to discuss tradeoffs in IoT designs? After the obligatory introductions, Ed Sperling took this group into questions on power, performance, and integration.… Read More


SoC QoS gets help from machine learning

SoC QoS gets help from machine learning
by Don Dingee on 07-29-2016 at 4:00 pm

Several companies have attacked the QoS problem in SoC design, and what is emerging from that conversation is the best approach may be several approaches combined in a hybrid QoS solution. At the recent Linley Group Mobile Conference, NetSpeed Systems outlined just such a solution with an unexpected plot twist in synthesis.

The… Read More


Webinar alert – Smart homes demanding low power Wi-Fi

Webinar alert – Smart homes demanding low power Wi-Fi
by Don Dingee on 04-07-2016 at 4:00 pm

There are two camps of thinking on the IoT: those who believe Bluetooth and Wi-Fi rule the edge, and those who support any of dozens of other wireless networking specifications for their various technical advantages. The ubiquity of Wi-Fi in homes helps devices connect in a few clicks – so why don’t more IoT designers use it?… Read More


Fit-for-purpose IoT ASICs are about more than cost

Fit-for-purpose IoT ASICs are about more than cost
by Don Dingee on 04-06-2016 at 4:00 pm

We’ve been saying for a while that it looks like there is a resurgence in design starts for ASICs targeting the IoT. A recent webinar featuring speakers from ARM and Open Silicon (and moderated by Daniel Nenni) affirms this trend, and provides some insight on how these designs may differ from typical microcontrollers.

One of my first… Read More


Optimizing memory scheduling at integration-level

Optimizing memory scheduling at integration-level
by Don Dingee on 04-04-2016 at 4:00 pm

In our previous post on SoC memory resource planning, we shared 4 goals for a solution: optimize utilization and QoS, balance traffic across consumers and channels, eliminate performance loss from ordering dependencies, and analyze and understand tradeoffs. Let’s look at details on how Sonics is achieving this.… Read More


4 goals of memory resource planning in SoCs

4 goals of memory resource planning in SoCs
by Don Dingee on 03-21-2016 at 4:00 pm

The classical problem every MBA student studies is manufacturing resource planning (MRP II). It quickly illustrates that at the system level, good throughput is not necessarily the result of combining fast individual tasks when shared bottlenecks and order dependency are involved. Modern SoC architecture, particularly … Read More