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Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one? That’s a great question, so I took some time at #53DAC in Austin to listen to one EDA vendor share their approach inside the TSMC booth where Open Innovation Platform (OIP) companies were making presentations. Michael Pronath from MunEDA was able to present 22 slides in about 20 minutes, so I’ll give you my recap in this blog.

Semiconductor IP using full-custom design and layout techniques are typically found in high volume applications or high-performance functions like:

  • Memory (NVM, Flash, DRAM, SRAM)
  • Custom Cells (datapaths, register files, PHY, clock distribution)
  • RF (VCO, PLL, LNA, mixer)
  • AMS (voltage reference, amplifiers, data converters)

As management asks the design team to migrate from one node like 28nm to another node like 16nm, then there’s a lot of work involved because you have to consider the impact of process variation on the design yield, how aging and reliability effect reliability at the smaller node, and how to achieve the best PPAC (Power, Performance, Area, Cost) in the time allotted. In the pure digital world the designers typically use logic synthesis, try some floorplanning, run some STA and iterate until timing closure is reached. In the AMS and RF IP world life is not so simple when it comes to porting cells:

  • Change device sizes
  • Adjust geometries like MOS width and length
  • Update biasing
  • Meet new specifications
  • Verify new Vdd levels

An approach used at MunEDA to automate this process uses the concept of specification-driven IP porting. Here’s a quick flow showing how you can start this process with your old schematic and prior PDK models, adding the new PDK models and using the Schematic Porting Tool (SPT):

So this SPT software lets you define how to replace devices from the source PDK with the new counterpart in the target PDK, giving you flexible property mapping and automating the shrinking. This happens for all device types: MOS, R, C and other properties. SPT even understands how to work with your hierarchical schematics. Why use an automated schematic porting process?

  • Correct and consistent replacement of device instances, no manual errors
  • Speed, 1,000s of devices migrated in just seconds
  • Multiple device types supported
  • Automated documentation on the porting results

Related blog – IC Design Optimization for Radiation Hardening

At DAC Michael showed an example of migrating a source schematic in Virtuoso that used TSMC N40 bulk process and then converted it into a 16nm FinFET process (TSMC N16). As the title of the blog promised, here are the three major steps involved with automated porting:


  • Schematic porting, IP re-use (circuit and process migration)
  • Design assessment (topology adjustment, simulations)
  • Sizing for sign-off (circuit analysis, optimization, verification)

    Circuit sizing and optimization is where the device parameters like Width and Length of MOS transistors are automatically selected in order to meet the circuit specifications for metrics like: Noise, jitter, speed, stability, power, area, robustness, yield, etc. You really want an automated approach here instead of a manual approach if you are under a deadline. MunEDA not only offers SPT, but it has an entire suite of tools called WiCkeD that are integrated and kind of push-button to operate.

    So how does this theory apply to actual circuits? Michael shared an example of a VCO designed in TSMC 65nm RF process that needed to have phase noise reduced, power consumption kept low, and reduce the effects of transistor mismatch. Using the WiCkeD software tools a fully automated sizing was done in a short time, reducing phase noise, and predicting high yield.

    Related blog – SRAM Optimization for 14nm and 28nm FDSOI

    Another example given was for an I/O level shifter block in TSMC 10nm FinFETtechnology where the designers needed to reduce sensitivity to process variation and Vdd variation. Using the three step approach they were able to optimize MOS widths to reduce corner spread of duty cycle and delays, running in under 10 minutes on one CPU. Corner spread was reduced by 50%.

    My first job out of college was working at Intel and I had to manually migrate a DRAM design from one process node to a smaller one, taking me at least a man-year of effort. If only I had tools like WiCkeD from MunEDA, then it would’ve made me work smarter instead of harder.

    Related blog – Design and Optimization of Analog IP is Possible

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