There is an old saying popularized by Mark Twain that goes “There are three kinds of lies: lies, damned lies, and statistics.” It turns out that no one can say who originated this saying, yet despite however you might feel about statistics, they play an important role in verifying analog designs. The truth is that there are large numbers of process parameters that can vary between chips and within a single chip. As much as foundries try to maintain consistency, there are variations that can affect chip performance and yield. It is absolutely necessary for project teams to understand the effects of these variations so they can determine product behavior and yield. Thus, statistical analysis becomes extremely important in the design process.
MunEDA is offering a webinar that reviews variation analysis methods and dives deeper into how they can be used efficiently to give designers what they need to ensure proper design performance. Michael Pronath, MunEDA Vice President of Products and Solutions provides a cogent introduction and summary of variation analysis methods. He starts with an overview that includes PVT corner analysis, Monte Carlo (MC) Sigma-to-Spec/Cpk, MC pass fail yield estimate and Worst Case Analysis (WCA) for yield optimization, design centering, high sigma analysis and hierarchical verification.
MunEDA’s WiCkeD Monte Carlo Analysis (MCA) comes with many features that make understanding the results much easier. Their results viewer shows the MC results and shows sigma levels against an ideal Gaussian fit. Complete statistical information is available for each design parameter in an easy to digest interface. MunEDA’s Quantile plot shows how well the results fit various parametric estimates. From this it is easy to see if the tails are long or symmetrical, etc. For each performance value, such as slew etc., users can look at the parameter influence analysis to see how sensitive they are to the process parameters. To help identify the source of sensitivities, they offer a view of hierarchical MC sensitivities that goes from block level to device or parameter level.
The real substance of the webinar is in the descriptions of the advanced Monte Carlo methods offered in MunEDA’s WiCkeD. We all know that the killing issue with MC is when it’s run brute force, huge numbers of simulations are needed to get meaningful results. For high sigma designs the number of runs required becomes astronomical. Over the last few decades tremendous progress has been made in devising methods to get meaningful results with much less time and resources.
Michael has a deep understanding of the methods and technology, so hearing him discuss the various approaches available in the MunEDA product line is fascinating and very intelligible. He goes through each of the following: quasi-random MC sampling, sequential sampling, scaled sampling, and combining PVT corners and MC sampling. I will not venture here to repeat or duplicate what he goes over. However, is it worth pointing out that the techniques he covers are extremely effective at saving analysis time by dramatically reducing the number of needed simulation runs.
Methods such as worst case analysis can even provide better results than what can be achieved with pure sampling methods. The methods also scale well for larger designs. Of course, MC was first used on memory cells, which were used many times in a single design, and were easy to simulate on their own. Now, much larger analog blocks and designs must be analyzed for yield and performance out to high sigma values because of high production volumes and high reliability applications.
This webinar really does a nice job of covering the available methods for statistical analysis. Maybe even enough to sooth those who have apprehensions about statistics. The webinar is scheduled for June 30th at 9AM Pacific Time. Be sure to register if you have an interest in this topic.