We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low power and it brings with it a completely new level of expectations, and design complexity.
Ultra low power is needed to run RFID, implantable devices, remote sensing platforms, or wearable tech. It needs to run with no built in power source, as is the case for RFID, or with very limited power, such as with small lithium polymer batteries charged by solar energy. The needs of ultra low power have pushed design methodology into new areas, like sub threshold CMOS analog design. With this shift in design comes the need for new tools to solve difficult design problems.
While digital designers are looking to drive their transistors into strong inversion rapidly to quickly move through the highly resistive transition that draws power and dissipates thermal energy, analog designers are interested in weak and moderate inversion modes so they can save power and achieve high gain – gm/Id. Threshold voltages have dropped to save power across the board, and analog designers are looking to operate their circuits at sub threshold voltages for a variety of reasons.
Circuits that operate in the moderate inversion region are very conducive to analog design. In fact gain values can exceed those of BJT’s, and thermal noise can be lower because of less carrier scattering. But care needs to be given to evaluate the effects of variation and the properly optimize the circuit to ensure operation in the region that was intended.
Designers end up with a complex multi-variable, multi-objective design problem that has many dimensions and tricky sensitivities. The old days of picking gate dimensions with a spreadsheet and running a few simulations to verify and fine tune the results are long gone. In fact simulation needs to move from being a verification tool to a design tool.
This is exactly what Munich based MunEDA was showing at #52DAC recently in San Francisco. I met with Michael Pronath VP of Products and Solutions at MunEDA to see a demo and discuss their solutions for optimizing analog circuits designed for ultra-low power. He used theoir WiCKeD suite to run through the flow on a Miller OpAmp operating at 1.2V. The design targets were: Phase Margin > 70, GBW = 1MHz and of course absolute minimum power. He used WiCKeD to optimize all the transistor W,L values, set the bias current, etc.
While maintaining all the design objectives Michael showed me how the design can be optimized with their Deterministic Nominal Optimization DNO to achieve the lowest power with all the transistors operating in moderate inversion. They can even add in process and thermal variation to be sure that the circuit is well behaved for high yield and reliability.
The results were impressive and showed an improvement over the classical and gm/Id methodology. Certainly gm/Id is a good method for evaluating transistor circuits in moderate inversion, but WiCKeD’s numerical sizing approach is good at optimizing yield and reliability, which are nearly impossible with other approaches with capacity constraints. WiCKeD works comfortably with:
- >100 specifications and constraints handled simultaneously
- >200 design variables
- >2000 MOS Post-layout effects and parasitics supported
- Multiple test benches, goals, and corners are considered
The user interface also allows designers to go through the flow by combining step visually to arrive at a set of alternatives to pick the best results.
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MunEDAhas quietly been collecting a large majority of the top semiconductor companies in its customer list. For me seeing the software in use helped clarify the operation and advantages of their unique approach. I can see why designers would like their approach for getting the lowest possible power out of sensitive designs.
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