At the beginning of every project the one of the first questions that ought to be asked is whether there blocks from previous designs that can be reused. On the surface this seems pretty obvious. The wrinkle in this is that reusability varies a lot based on the design type and the effort that a team is willing to expend to bring a design forward. HDL’s are at the top when it comes to reusability. There is always some messing with constraints and details, but moving an HDL based design to a new PDK is a well-trod path.
Probably at the other end of the spectrum are analog designs that are captured in schematic form. These are full of vexing idiosyncrasies and PDK specific nuances. In contrast to HDL based blocks, which remain largely intact during a porting exercise, schematics change both structurally and visually. But that is not all, schematic based designs need to have operational parameters optimized for their performance objectives in the new process.
A workable solution for schematic porting needs to be able to convert the design to the new library, adapt the visual representation and also facilitate optimization of the design to the new process. If any of these actions are problematic, schematic porting and subsequent reuse will become troublesome.
MunEDA has made a name for themselves with their advanced analog circuit optimization software, and also have put a lot of effort into their schematic porting solution, called SPT. This gives them the notable advantage of having a complete solution. Let’s look a little deeper at the features that the schematic porting tool offers.
MunEDA’s recently enhanced SPT automatically performs many operations that can make porting by hand tedious and that other porting tools may not handle. The GUI for MunEDA’s SPT is started from inside of Virtuoso. The user selects the source and target PDK’s for the design. SPT makes suggestions for each cell mapping based on cell names. Users of course can change the mappings any way necessary. Property and symbol mapping are handled in an elegant way with a set of mapping rules that can be applied to cells based on common traits. Having classes of property and symbol mapping rules reduces repetitive work when a set of cells are similar.
The mapping setup GUI makes it easy to see the results for each cell. There is built in intelligence to help deal with extra pins, symbols with different orientations and aspect ratios. For instance, after pins are mapped, SPT looks at the orientation of the symbol to determine what orientation is best for maintaining existing connections. There are more features like this; MunEDA has been doing this for a long time and SPT shows the benefit of their experience.
However, as mentioned above the real power of their solution comes from adding powerful analog circuit optimization capabilities to complete the porting task. MunEDA breaks this portion into four phases. First off, their optimization flow is used to fulfill constraints for the design. Then they can perform nominal optimization so specs are met at typical conditions. Then the MunEDA tools ensure that the design meets specs at worst case operating conditions. Finally, robustness is improved with their flow by taking into consideration process variation and mismatch.
All in all, a fairly automated process. Once it is set up for a design, the porting profile can be saved and reused on other blocks easily. MunEDA suggests that what took weeks previously can be accomplished in hours. This certainly is good news for anyone embarking on a project that intends to reuse designs from other fabs or process nodes. The MunEDA website has more information on their schematic porting tool and circuit optimization tools.