Accelerate Early Design Verification for faster Time to Market

Accelerate Early Design Verification for faster Time to Market
by Admin on 06-25-2020 at 11:00 am

Register For This Web Seminar

Online – Jun 25, 2020
11:00 – 12:00 IST

Overview

Advanced nodes brings in complexity in designs leading to high Physical verification times with increasing number of DRC errors and more verification iterations. Calibre responds to the need for reduced cycle time with revolutionary

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Addressing Structural Challenges Through Design Exploration

Addressing Structural Challenges Through Design Exploration
by Admin on 06-16-2020 at 11:00 am

June 16, 2020

11:00 AM (EDT)

Venue:
Online

Structural assemblies are often very intricate with complex interactions between components, which are challenging to manage in traditional simulation applications. In this webinar we will explore design iterations through upfront Ansys Discovery simulations to optimize performance

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Webinar: An Intelligent System Design Platform for Chiplet-Based Architectures

Webinar: An Intelligent System Design Platform for Chiplet-Based Architectures
by Admin on 05-27-2020 at 10:00 am

Date and Time

Wednesday, May 27, 2020
Time: 10:00am – 11:00am (PDT)

Providing the best alternative to advanced monolithic SoCs, multi-chiplet packages have become a very attractive option for the next generation of cost-sensitive designs. However, as many engineers begin to realize the benefits of a multi-chiplet packaging

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Effect of Design on Transistor Density

Effect of Design on Transistor Density
by Scotten Jones on 05-26-2020 at 10:00 am

TSMC N7 Density Analysis SemiWiki

I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes… Read More


Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Admin on 03-24-2020 at 11:00 am

Tue, Mar 24, 2020 11:00 AM – 12:00 PM MDT

*** This vendor requires that you register with your work email address ***

As designs migrate to cutting edge single digit nanometer technologies, designing high yielding products that quickly enter the market is key to remain competitive in the chip industry. Advanced node digital… Read More


How to Design and Validate with AEC Grade 0

How to Design and Validate with AEC Grade 0
by Admin on 03-04-2020 at 11:00 am

March 4, 2020

12:00PM – 13:00PM (EST)

Venue:
Online

As the automotive industry undergoes radical transformation with electrification and autonomy, there is an increasing need for semiconductor devices that last longer and can operate at higher temperatures. In response, the Automotive Electronics Council (AEC) released

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MEMS Actuation and the Art of Prototyping

MEMS Actuation and the Art of Prototyping
by Bernard Murphy on 11-27-2019 at 5:00 am

Thermal actuator prototyping

I mentioned a while back that I’m really getting into the role that sensors play in our new hyper-connected world – in the IoT, intelligent cars, homes, cities, industry, utilities, medicine, agriculture, etc, etc. If we can think of a way to sense it and connect it, someone is probably already doing it. But there’s more to … Read More


Mentor-Tanner Illuminate MEMS Sensing, Fusion

Mentor-Tanner Illuminate MEMS Sensing, Fusion
by Bernard Murphy on 08-14-2019 at 6:00 am

I enjoy learning and writing about new technologies closely connected to our personal and working lives (the kind you could explain to your Mom or a neighbor). So naturally I’m interested in AI, communication and security as applied to the home automation, transportation, virtual, augmented and mixed reality, industry and so… Read More


At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More


Solving and Simulating in the New Virtuoso RF Solution

Solving and Simulating in the New Virtuoso RF Solution
by Tom Simon on 10-30-2018 at 12:00 pm

Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More