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Photolithography is the most critical and is typically controlled to + or - 1%, the rest of the fab is more like + or - 5%.
Humidity is monitored and controlled in real time by the facility management system. For large fabs with a centralized control room it would be monitored there. In modern...
With respect to yield, the defect density is based on electrical test of test chips designed to the pdk, I think the basic idea is the pdk is supposed to define all the design rules you need to meet to yield to the extracted defect density, but they aren't perfect and get updated periodically...
There are two fundamental problems with characterizing processes using the blocks you outline above.
1) Each block density will depend on the process and the design, not just the process. Two different designs with different design goals done on the same process can have very different...
You are misunderstanding the methodology, there isn't a "standard number of fins", you have to do the whole analysis for each process/node.
First, you have to take into account diffusion break, the 2-input NAND and Scan Flip Flop width depend on diffusion break. Everyone is using the same...
See my post above, BPD is more expensive and the mobile guys don't need it and don't want to pay for it. I am hearing the foundries will have to offer with and without BPD plus different metallization schemes.
It can also be dramatically cheaper because you don't need 17+ interconnect layers. I haven't seen any of the big logic companies talking about dedicated SRAM processes, maybe as ChipLets catch on it will generate interest.
“TSMC said that 4.2 GHz speed was for the HC array not the HD array.”
I looked at the paper specifically to determine whether is was HD or HP/HC. On slide 27 they show the test chip and specifically say it is HD, slide 28 and 29 show Vmin plots and again say HD, slide 30 is the Shmoo plot and...
The 2x is for the fab construction and doesn't include tools. I didn't think it was that big a difference either and I got a bunch of expert inputs when I wrote my operating cost comparison article a few year ago. I think things may have changed post COVID, I am looking into it.
I have a bunch of comments on this thread I am going to roll into one big comment.
With respect to the Fmax Shmoo plots, what isn’t obvious until you read the papers is TSMC’s array is HD cells (plus double pumped although I don’t think that matters for clock speed). Intel’s array is HP cells...
Everyone was thinking Ruthenium (Ru) but then they woke up to how expensive it is. My belief is Molybdenum (Mo) for vias first and then critical interconnect over the next several years. Mo is reasonably inexpensive, almost as low resistance at small dimensions as Ru, can be barrierless and can...
TSMC released their 2024-Q2 results today and I went through my proprietary analysis. I see no evidence that 5nm equipment dropped off being depreciated yet.
I reached out to sources with direct knowledge of how the start of depreciation is handled at Semiconductor companies, see my post above.
Yes "Depreciation of an asset begins when it is available for use" but there is some interpretation that goes into "available for use".
I reached out to multiple sources with direct knowledge of when depreciation starts.
Yes, the standard is: "Depreciation of an asset begins when it is available for use" but what does this mean in practice?
In drug manufacturing you can have an entire facility ready to go but you don't start...
As I said elsewhere Intel is not the only company to change their depreciation period, I can pretty much guarantee they checked with their auditors before doing that.
I have no idea where your intentionally delayed depreciation comment comes from.
"Depreciation of an asset begins when it is available for use".
That is not consistent with my understanding and not consistent with my analysis of their financials. When they buy an asset it goes into assets in progress and stays there not depreciating until they put it on-line.
Intel is certainly not the only company to do this. Micron extended depreciation on their DRAM equipment to 7 years in 2016 and then to 7 years on their NAND equipment in 2020.
There are two ways to looks at this.
From a balance sheet perspective if you put $1B of equipment on line, the first year your write off $200M and have $800M left, the second year you write of $200M and have $600M left, etc. So in that sense by the end of the third year it is more depreciated...
