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Search results

  1. S

    Updating our current logic density benchmarking methodologies

    "As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
  2. S

    How is backside power really done?

    The connection is from the side just like for the Power Via. "As a side note why do you think that AMAT and intel have a different definition of what BPR is from IMEC? The engineers from both firms are far from dummies, and they both contribute to IMEC. The difference in opinion and definition...
  3. S

    How is backside power really done?

    Imec tells me the AMAT diagram you used is incorrect with respect to BPR and it connects from the side, not up through metal 0.
  4. S

    How is backside power really done?

    My understanding is the process is: 1) Transistor formation and front side interconnect formation on the front of the device wafer. 2) A carrier wafer is bonded to the front of the device wafer. 3) The wafer pair is flipped over and most of the device wafer is removed from the back. 4) Through...
  5. S

    Will VTFET become the new chip technology?

    We are running 3nm now with 2nm (20A) due 2024 to 2026 depending on version and company. Samsung has talked about 1.4nm in 2027 based on a Horizontal Nanosheet with more sheets. My projections are 10A around 2029 based on a CFET, with 7A, 5A, and 3A CFETs to follow. Finally around 2037 we get...
  6. S

    Will VTFET become the new chip technology?

    High density logic cells in TSMC 3nm are just under 300MTx/mm2.
  7. S

    Will VTFET become the new chip technology?

    Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
  8. S

    Will VTFET become the new chip technology?

    The authors are a bunch of academics, it is an interesting intellectual exercise but I would be shocked if this ever saw the light of day.
  9. S

    Will VTFET become the new chip technology?

    It not quite 2x density due to interconnect requirements but it is a big jump. 2D gives a big jump in CPP and therefore cell width, and CFET gives a big jump in cell height by doubling up the transistors and eliminating the horizontal n-p spacing. My estimate is 1,500 MTx/mm2 in 2037.
  10. S

    Will VTFET become the new chip technology?

    Do you have a reference for that demonstrator, I have never heard of that and never heard/seen anyone talk about it and I am very plugged in to that community.
  11. S

    Will VTFET become the new chip technology?

    As is CFET and both Intel and TSMC have published on it extensively and both have shown slides with CFET as a post HNS option. Neither has talked about VTFET.
  12. S

    Will VTFET become the new chip technology?

    My own, I have been analyzing this path for many years, I have a presentation of over 60 slides that walks through the whole path and has been shared with/reviewed by a select group of experts.
  13. S

    Will VTFET become the new chip technology?

    It is nanosheets rotated 90 degrees. I don't see this as stackable and it isn't a CFET. It looks to me like the vertical nanosheet would be lithographically defined and that has more variability than the epitaxially defined horizontal nanosheets (HNS). As I noted above I don't see this as...
  14. S

    Will VTFET become the new chip technology?

    Once you make the change from FinFETs to Horizontal Nanosheets (HNS) you open up a scaling path that will carry us for over ten more years of logic scaling. First there will be multiple generations of HNS, then multiple generations of CFET, and eventually 2D material CFETs. We are currently at...
  15. S

    Will VTFET become the new chip technology?

    "VTFET main allure is the "free" path to monolithic 3D, which horizontal devices don't have." How did you come to the conclusion that this is a stackable technology? It's not clear to me that this is stackable and that isn't what the paper discusses as the advantage of this technology.
  16. S

    TSMC Pioneers Joint Procurement of Renewable Energy to Strengthen Suppliers' Carbon Reduction Capabilities

    So what is your position, the problem is China and nothing else matters? What do you think should be worked on? The other point here is even if you don't think semiconductors matter, TSMC does or they wouldn't have published this statement. I can also tell you I interact with a who's who of...
  17. S

    TSMC Pioneers Joint Procurement of Renewable Energy to Strengthen Suppliers' Carbon Reduction Capabilities

    Of course China as a country uses more electricity than TSMC and their electricity has a high carbon footprint, but per KWh Taiwan is now even worse. In order to prevent catastrophic climate change real improvement is needed in every country and every industry. This is a site about...
  18. S

    TSMC Pioneers Joint Procurement of Renewable Energy to Strengthen Suppliers' Carbon Reduction Capabilities

    In Taiwan TSMC hardly uses any renewable energy, they primarily use the Taiwan power grid and that has some of the highest carbon emissions in gCO2e/KWh in the world. They do have the Ark power agreement that may be an important improvement but I haven't dug into that enough to know yet...
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