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Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 09-21-2021 at 10:00 am

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness that times have changed, and circuit designers can work smarter by using EDA tools that size transistors to meet goals, without all of that manual sizing and SPICE iterations.

I’ve been following EDA vendors with transistor sizing tools for many years now, and MunEDA has this technology. They are hosting a webinar on September 28th, 9AM – 10AM PDT, with the title, Optimal Circuit Sizing Strategies for Performance, Low power, and High Yield of Analog and Full-custom IP. You can catch the replay HERE.

I asked some questions about their circuit sizing technology to learn more, prior to the webinar.

Circuit Sizing Q&A

Q: Does the circuit sizing work for any IC technology: Planar CMOS, FinFET, GAA, Bipolar, BiCMOS, SiC ?

Yes, the optimization algorithms we are using for circuit sizing are developed and adapted to all today typical semiconductor process technologies like the ones mentioned by you. This is enabled by smart combinations of continuous and discrete sizing methods that have been continuously improved with process generations over the years and are meanwhile highly applicable and efficient.

Q: How large of an IP block can I optimize sizes for, in terms of MOS transistors and Resistors?

There is not really a limit by the number of single devices in your circuit. Nevertheless circuit sizing is more practical when you have circuits or blocks with a reasonable simulation time that lasts from a few seconds to a few minutes for a single simulation. Typical IP blocks used for sizing and optimizing are between a few dozen up to several hundred devices large. You have to consider that a nominal optimization run requires typically a few hundred simulations, a full yield optimization including worst-case and degradation effects can require a few thousand simulations. Depending if you expect a result within 1-2 hours or can run the optimization over the weekend or for a whole week, will have great influence on which circuits or even whole chips can be useful for such optimization runs.

Q: Do I use my own SPICE circuit simulator along with your optimization tool?

MunEDA’s tools are simulator-agnostic which means they are integrated and run with the standard industrial SPICE simulators from the large simulator vendors. But we also have integrated and run our tools with customers’ in-house simulators for many years. We are not urging the customer to use a specific simulator to run our tools. Customers like to work in their individual, quality-proven and certified design framework and simulation environment, in which other tools like MunEDA’s should be integrated smoothly and seamlessly. This is given and guaranteed for MunEDA tools for enhanced circuit migration, verification and optimization.

Q: Does your approach take advantage of multi-core CPUs?

Yes, all simulation runs can be parallelized over a network and run simultaneously on parallel simulation engines using multi-core CPUs for further speed-up.

Q: Can I run optimization in the cloud as a service?

MunEDA is offering the EDA tools for doing automated migration, verification, sizing and optimization for direct installation with our customers. We are not offering optimization services in the cloud, but our customers can install and use our software in the cloud. In reality it is often the case that our customers, fabless design houses or IDM Integrated Device Manufacturers are working with our tools to migrate their own or their customers IP from existing foundry process to new process technologies. After migration running circuit optimization can help to address the new customer specifications for the transferred IP much faster and more efficient.

Q: Is your sizing technology patented?

We have no patents on our sizing technology. There are many publications around about circuit sizing and optimization, but only a very few EDA vendors have managed to successfully implement these complex methods into such easy to use tools like MunEDA.

Q: Has there been correlation with silicon results to prove that the sizing was optimized, or do we just compare SPICE simulation results?

We have many cases about this, some of them have been published by our customers on our regular MUGM MunEDA User Group Meetings. Customers will compare correlations of both simulation runs and silicon runs with each other. Our methods and software can often also detect if there are problems with technology data in the PDK. Also comparison between PCM measurements and simulation data can be checked with our tools. This helps the designer but also the process engineer to get higher confidence about effects that can happen in between simulation and manufacturing of circuits and chips.

Q: What is the learning curve like for your circuit sizing tool?

It is often quite easy and not very hard. The circuit designer knows her/his circuit often quite well. Therefore, also performances, specifications and other important target lines are often known. The designer simply defines such sizing and optimization targets in the tool – can be also partially imported from the design framework – and starts to run the optimization algorithms. The sizing tool takes into account all constraints and circuit restrictions and tries to optimize for the given circuit as much as possible. The optimization procedure follows here exactly the structure the designer knows from manual design optimization like constraint check and optimization, performance optimization, worst-case corner optimization, optimization for statistical variation and yield, and even degradation and reliability effects. The setup routine is fast and easy and the optimization itself can run automatically in the background without much designer attention. As all tools can be run by an easy to use GUI Graphical User Interface but also in batch mode the designer can select its preferred way of working easily.

Q: Are the optimization results displayed numerically, graphically or both?

The optimization results will be always available in both ways. But more than this you also can compare the values and curves with the waveform extracted from the SPICE simulations. The designer can also see easily how much trade-offs are still in the circuit to improve them further (e.g. for less area, less power or higher performance and speed). There are many GUI and display functions the designer can get information out of the tools that helps for her/his design and quality reports. There are numerous export and printing functions you can transfer the results to other tools.

Q: Can I optimize for both time-domain and frequency-domain analysis?

Yes this ca be done simultaneously running the same DUT device-under-test within different domains using our powerful multi test bench environment.

Q: How do I control the optimization process, are there any settings that I need to learn?

You can directly follow in the GUI the changes the tool is doing during the optimization process on your circuit performances or other parameters. There are also graphs.

Q: How is ML applied during circuit sizing?

Our sizing methods contain highly intelligent ML-based decision algorithms that continuously measure and simulate the current status and automatically calculate directions for improving the circuit in the desired way. For this reason the designer attention during the sizing and optimization process can be reduced to an absolute minimum. The ML-based algorithms also can run circuit optimization for the same test-bench under various also sometimes controversial conditions.

Q: Who are some of the customers using your circuit sizing?

Our circuit sizing algorithms are in use by numerous large, midsize and small IDM integrated device manufacturer, fabless design and IP houses but also by the IP and design services departments of silicon foundries. We have numerous publications and presentations from our customer such as Samsung, STMicroelectronics, SKHynix, Infineon, Novatek, ROHM, Fraunhofer, inPlay, SMIC, and many others from our MUGM MunEDA User Group Meeting but also international conferences such as DAC, CICC, ANALOG and others.

Q: How does the circuit sizing optimization take into account all of the layout parasitics?

After layout you can run our highly-efficient circuit sizing tools to run on the extracted and flat netlists to check on the parasitics and reduce their influence by very small sizing steps especially to improve the final yield and reduce the sensitivity to statistical process variations.

Q: Can a Junior IC circuit designer be successful with your tool, or do I need to be a Senior IC circuit designer?

All designers can easily run our tools for circuit migration, verification, sizing and optimization regardless if they have only a few or many years of experience. They are in use with graduate students or PhD students in universities, just like with design fellows at industrial semiconductor design and manufacturers. Our GUI-based alternative of step-by-step improvements or fully-automatically circuit sizing delivers this knowledge to the designer and adapts to her/his individual experience level.

circuit sizing min

Summary

Learn how to automate the circuit sizing portion of your transistor-level IC designs to get the best performance in a reasonable amount of time at this webinar on September 28th, from 9:00AM to 10:AM PDT. Watch the replay HERE.

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