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Automating and Optimizing an ADC with Layout Generators

Automating and Optimizing an ADC with Layout Generators
by Daniel Payne on 08-24-2022 at 10:00 am

I first got involved with layout generators back in 1982 while at Intel, and about 10% of a GPU was automatically generated using some code that I wrote. It was an easy task for one engineer to complete, because the circuits were digital, and no optimization was required. In an IEEE paper from the 2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, there was an article authored by experts from Fraunhofer IIS/EAS, MunEDA, IMST Gmbh and Dresden University of Technology. I’ll share what I learned from their article, “A Multi-Level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models.”

Analog designs like an ADC require that you start with a transistor-level schematic, do an initial IC layout, extract the parasitics, simulate, then measure the performance to compare against the specifications. This manual process is well understood, yet it requires iterations that can take weeks to complete, so there has to be a better approach. In the paper they describe a more automated approach, built upon three combined techniques:

  • Template-based generator
  • Parasitic estimation from object-oriented templates
  • Fast model-based simulation

The following diagram shows the interaction and flow between optimization, performance estimation and layout generators for an ADC:

Layout Geneator tool flow min
Generator Template, Model, Performance Estimation

There’s a SystemC AMS model of the pipeline ADC circuit, and the parameters define things like the number of device rows, while the model defines the behavior of non-ideal capacitors and OpAmp offsets. The flow is designed to be executed, and when optimized it reaches an acceptable performance criteria.

The inner loop makes an estimate of the layout parasitics in about 5 seconds, and then the ADC is optimized and a layout generated in about 1 minute. The layout generator uses the best parameter set, and generates the capacitor structures. Layout capacitance values for device and wires were pre-characterized to enable fast estimates in the template approach. The optimization step is using estimated parasitics, not extracted parasitics, saving time.

A SystemC AMS model of a pipeline ADC has both behavioral and structural details, so that engineers can trade off accuracy versus runtime. Using an analytical model enables a thousand runs in just a few minutes. The outer loops adds the ADC model, and that run takes about 50 seconds to complete.

This generator template approach even estimates layout parasitics, capacitor variation and device mismatch. Both global and local process variations were taken into account.

Results

Starting from transistor-level schematics for the ADC, a parameterized model was built. Having a model enabled fast simulation and optimization, with the goals of:

  • Reduced layout area
  • Specific layout aspect ratio
  • Minimal error in the effective capacitor ratio
  • Robustness against process variations and mismatch

Layout-level optimization used an EDA tool from MunEDA called WiCkeD, which has a simulator in a loop approach, and the template was the simulator:

WiCkeD optimizer min 1
Optimization with WiCkeD

As the optimizer needs to find the performance for a set of design parameters, it asks the template to evaluate them. The optimizer finds the direction to change the design parameters that improve the layout. Evaluating a template takes under 5 seconds, so the optimization can quickly reach an optimal set of layout parameters.

To get the best capacitor array aspect ratio they selected an input parameter range of W and L for the unit devices, and the number of rows in the array. Next, they simulated the worst-case performance, including offsets in under two hours with 114 individual parameterizations. The worst-case transfer functions of the ADC model, based on numbers of rows in the capacitive array and various W over L values are shown below, where the ideal curve is dashed:

Worst case transfer functions min
Worst-case transfer functions

Summary

Analog design and optimization is more difficult than digital design, because there are more interdependencies and trade-offs involved. A new approach with layout generators, template-based layout estimates and optimization has been demonstrated successfully for an ADC circuit, and it uses optimization technology from MunEDA, called WiCkeD. Instead of taking days to weeks, this approach met specifications for an ADC in just minutes.

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