WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration

WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration
by Daniel Nenni on 11-01-2023 at 6:00 am

AVFS IP SOC

Today’s power modeling solutions are trained at measuring power using the micro-events captured from detailed RTL simulation or studying the electromagnetic radiation from IR drop and side channel attacks. These solutions are fantastic for debugging and verification of the implementation. There are both open source and … Read More


Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging

Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging
by Admin on 08-31-2023 at 2:05 pm

Date: September 15, 2023 (Friday) 15:00-16:00

Organizer:

Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: September 14th

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The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am

Figure 3

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More


AMIQ: Celebrating 20 Years in Consulting and EDA

AMIQ: Celebrating 20 Years in Consulting and EDA
by Daniel Nenni on 07-06-2023 at 10:00 am

AMIQ20

We’re getting close to the annual July Design Automation Conference (DAC) in San Francisco, and every year I like to make the rounds of the exhibitors beforehand and see what’s new. When I checked with AMIQ EDA, I found that this is a big year for them. Their parent company AMIQ just reached its 20th anniversary, and they’ll be celebrating… Read More


The State of IC and ASIC Functional Verification

The State of IC and ASIC Functional Verification
by Daniel Payne on 02-09-2023 at 10:00 am

Silicon Spins min

Way back in 2002 there was a study from Collett International Research on functional verification, and since 2010 the Wilson Research Group has continued that same kind of study with a new report every two years. What attracts me to this report is that it doesn’t just look at the installed base of one EDA vendor, instead it looks… Read More


Rethinking the System Design Process

Rethinking the System Design Process
by Daniel Nenni on 12-08-2022 at 10:00 am

Rethinking the System Design Process 1

The system design process can incorporate linear thinking, parallel thinking, or both, depending on the nature of the anticipated system, subsystem, or element of a subsystem. The structure, composition, scale, or focal point of a new/incremental system design incorporates the talents and gifts of the designer in either a … Read More


Webinar: The Keys to SystemC & TLM-2.0

Webinar: The Keys to SystemC & TLM-2.0
by Admin on 09-14-2022 at 1:48 pm

Friday September 23 2022

1 hour session (All Time Zones)

Presenter:

David C Black

Senior Member Technical Staff

Asia and Europe

Friday, September 23, 2022

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)

Americas

Friday, September 23, 2022

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

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