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Numerical Sizing and Tuning Shortens Analog Design Cycles

Numerical Sizing and Tuning Shortens Analog Design Cycles
by Tom Simon on 11-22-2021 at 6:00 am

By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent process. The webinar titled “Optimal circuit sizing strategies for performance, low power, and high yield of analog and full custom IP” describes the problems designers encounter and offers a solution.

Memories, custom cells, RF and analog blocks are facing challenges that include smaller process nodes, difficult PPA trade-offs, reliability, low noise requirements, yield, etc. Equation-based circuit sizing can become intractable, especially when numerous performance specifications are added to the problem. It quite quickly becomes an expanding n-dimensional problem. Not only is it hard to find a working solution through manual iteration, manual approaches often prevent significant further optimization from being achieved. In many cases Michael explains reaching the optimal value of one spec violates another spec. This can arise from non-linear parameter dependencies resulting in mixed effects. He suggests that it’s not enough just to shift nominal values, but instead sensitivities need to be minimized so that yields can be improved.

Sizing and tuning
Sizing and tuning

MunEDA has developed an automated tool that performs numerical resizing based on simulation results to refine device parameters to achieve all of a design’s specifications. The initial design needs some initial sizes, but even if it does not meet all design specs, MunEDA’s circuit sizing, optimization and variation analysis tools can find optimum results, or tell the designers that a different topology is necessary. MunEDA’s WiCkeD Tool Suite delivers performance optimization over multiple PVT corners on all test benches simultaneously. It is smart enough to perform automatic analog structure recognition. It performs yield optimization, and power & area optimization. It is suitable for traditional process technologies and FinFET nodes. As the WiCkeD tools work on a design they keep a design history and database at each step, so it is easy to perform experimentation and exploration.

MunEDA’s automated numerical circuit sizing with WiCkeD progresses through four distinct stages. Feasibility optimization locates the design with correct DC biasing for MOS devices. Nominal tuning at typical PVT fulfills specs at typical conditions. Worst case operating conditions are met through tuning at different PVTs. Design centering is done to improve the robustness of the design against process variation and mismatch. Each phase narrows down the design parameters to achieve the best result.

After this discussion Michael moves the webinar on to a thorough demo that shows in detail how designers interact with the tool as they go through a design. There were several interesting highlights during this part of the webinar. The user interface provides both text and graphic feedback on the design state and performance. There is a fascinating view of the design that shows pairwise dependencies between specs so it is easy to comprehend where trade-offs might be difficult or easy to make. At each step of the sizing, tuning and optimization process there are graphs available that show values for each specification.

Michael runs through a convergent process of fitting specifications and moving toward completion. Frequently a process that might have taken weeks through manual optimization can be completed in several hours – including setup. The design history allows reverting to earlier steps and repeating them with different goals to find the best result.

Michael concludes with several case studies of customer designs where the WiCkeD Tool Suite has delivered impressive results. He shows a high speed DDRx IO, a PA core & filter, and a rail to rail input push-pull output AMP. In each of these examples the design time was reduced from weeks to hours and the PPA often was better than the by-hand results by a wide margin.

Michael’s expertise shows though in this concise but detailed talk on how to improve analog circuit design efforts. Breaking the bottleneck on analog circuit sizing and tuning can have meaningful result in shortening time to tape out. The webinar is available to view on-demand at the MunEDA website.

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