Webinar: Post-layout Circuit Sizing Optimization

Webinar: Post-layout Circuit Sizing Optimization
by Daniel Payne on 09-29-2022 at 4:00 pm

IC design workflow min

My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore, thanks to EDA tools that are quicker and more accurate than manual methods. MunEDA is an EDA vendor that has developed… Read More


Webinar: Simulate Trimming for Circuit Quality of Smart IC Design

Webinar: Simulate Trimming for Circuit Quality of Smart IC Design
by Daniel Nenni on 03-23-2022 at 6:00 am

p1

Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more.

However, more aggressive time-to-market and higher performance… Read More


WEBINAR: Simulate Trimming for Circuit Quality of Smart IC Design

WEBINAR: Simulate Trimming for Circuit Quality of Smart IC Design
by Daniel Nenni on 02-23-2022 at 11:14 am

Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more.

However, more aggressive time-to-market and higher performance… Read More


Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP

Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP
by Admin on 01-26-2022 at 12:29 pm

*COMPANY EMAIL IS REQUIRED FOR REGISTRATION*

Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips at the lowest costs. Efficient design for yield is a key capability … Read More


WEBINAR: Efficient and User-Friendly Analog IP Migration

WEBINAR: Efficient and User-Friendly Analog IP Migration
by Daniel Nenni on 11-25-2021 at 9:32 pm

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing.

While there can be many potential business motivations for any of the above, in today’s environment… Read More


WEBINAR: Using Design Porting as a Method to Access Foundry Capacity

WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
by Tom Simon on 11-24-2021 at 8:00 am

Schematic Porting the NanoBeacon

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More


Numerical Sizing and Tuning Shortens Analog Design Cycles

Numerical Sizing and Tuning Shortens Analog Design Cycles
by Tom Simon on 11-22-2021 at 6:00 am

Sizing and tuning

By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More


WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis

WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis
by Daniel Nenni on 06-04-2020 at 7:33 am

Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Designers must verify and characterize their IP’s sensitivity… Read More


Webinar on Tools and Solutions for Analog IP Migration

Webinar on Tools and Solutions for Analog IP Migration
by Tom Simon on 03-17-2020 at 10:00 am

MunEDA flow for analog design porting

The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog… Read More


Analog IP Migration, Optimization and Verification

Analog IP Migration, Optimization and Verification
by Admin on 03-14-2020 at 2:42 am

Thu, Mar 26, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**

ABSTRACT: Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible,… Read More