Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP

Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP
by Admin on 01-26-2022 at 12:29 pm

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Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips at the lowest costs. Efficient design for yield is a key capability … Read More


WEBINAR: Efficient and User-Friendly Analog IP Migration

WEBINAR: Efficient and User-Friendly Analog IP Migration
by Daniel Nenni on 11-25-2021 at 9:32 pm

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing.

While there can be many potential business motivations for any of the above, in today’s environment… Read More


WEBINAR: Using Design Porting as a Method to Access Foundry Capacity

WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
by Tom Simon on 11-24-2021 at 8:00 am

Schematic Porting the NanoBeacon

There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More


Numerical Sizing and Tuning Shortens Analog Design Cycles

Numerical Sizing and Tuning Shortens Analog Design Cycles
by Tom Simon on 11-22-2021 at 6:00 am

Sizing and tuning

By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More


WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis

WEBINAR: Analog Verification and Characterization with Monte Carlo and High-Sigma Analysis
by Daniel Nenni on 06-04-2020 at 7:33 am

Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Designers must verify and characterize their IP’s sensitivity… Read More


Webinar on Tools and Solutions for Analog IP Migration

Webinar on Tools and Solutions for Analog IP Migration
by Tom Simon on 03-17-2020 at 10:00 am

MunEDA flow for analog design porting

The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog… Read More


Analog IP Migration, Optimization and Verification

Analog IP Migration, Optimization and Verification
by Admin on 03-14-2020 at 2:42 am

Thu, Mar 26, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**

ABSTRACT: Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible,… Read More


56th DAC – In Depth Look at Analog IP Migration from MunEDA

56th DAC – In Depth Look at Analog IP Migration from MunEDA
by Tom Simon on 07-31-2019 at 10:00 am

Every year at DAC, in addition to the hubbub of the exhibit floor and the relatively short technical sessions, there are a number of tutorials that dive in depth into interesting topics. At the 56th DAC in Las Vegas this year, MunEDA offered an interesting tutorial on Analog IP migration and optimization. This is a key issue for large… Read More


A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation

A Practical Approach to Modeling ESD Protection Devices for Circuit Simulation
by Tom Simon on 06-03-2019 at 8:00 am

Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation. Accordingly, SPICE models for Mosfets do not behave well when the BJT is triggered. However, these models work just fine for most purposes. The one important… Read More


Ten Things to see @ 56th DAC!

Ten Things to see @ 56th DAC!
by Daniel Nenni on 06-01-2019 at 8:00 am

New products always take precedence since EDA is a “mature” market. I have inside knowledge on this one so I can tell you it is not to be missed. Coincidently, but not really, a related white paper was just published so if you are not going to 56thDAC you can still get a virtual briefing. If you are going to DAC be sure and stop by the Fractal… Read More