Webinar – Low Power Circuit Sizing for IoT

Webinar – Low Power Circuit Sizing for IoT
by Tom Simon on 05-19-2017 at 7:00 am

Optimizing analog designs has always been a difficult and tricky process. Designing for IoT applications has only made this more difficult with the added importance of minimizing power. Unlike other circuit parameters, it is not easy to specify power as a design goal when using equations. Power is a resultant property and must… Read More


Analog, Low-power Optimization at SMIC

Analog, Low-power Optimization at SMIC
by Daniel Payne on 01-11-2017 at 12:00 pm

Talking with actual IC designers is always fascinating to me, because these engineers are the unsung heroes that enable our modern day world of consumer and industrial electronics. Too often we only hear from the CEO or other C-level executives in the press about their own companies, products, services and vision. I recently had… Read More


Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More


SRAM Optimization for 14nm and 28nm FDSOI

SRAM Optimization for 14nm and 28nm FDSOI
by Daniel Payne on 05-16-2016 at 4:00 pm

I’ve done SRAM and DRAM design before as a circuit designer from 1978-1986, but in 2016 there are so many more challenges to using 28nm and 14nm on FDSOI technology. One way to keep abreast of SRAM design is to read conference papers, so I just finished a paper from authors at STMicroelectronics and MunEDA presented at the IEEE… Read More


IC Design Optimization for Radiation Hardening

IC Design Optimization for Radiation Hardening
by Daniel Payne on 03-28-2016 at 7:00 am

I was born in 1957, the same year that the Soviets launched the first satellite into Earth orbit, officially starting the Space Race between two global super powers. Today there are many countries engaged in space research and I just read about how engineers at IEAv (Institute for Advanced Studies) in Brazil did their IC design optimization… Read More


Tuning Analog IP for High Yield at SMIC

Tuning Analog IP for High Yield at SMIC
by Daniel Payne on 12-29-2015 at 12:00 pm

Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang,… Read More


Variation Aware FinFETs are Critical!

Variation Aware FinFETs are Critical!
by Daniel Nenni on 12-18-2015 at 4:00 pm

As I mentioned in “EDA Dead Pool” acquisitions in our industry will continue at a rapid pace. The latest victim is 10 year old French company Infiniscale who was recently purchased by Silvaco. This was more of a “let’s put your product through our massive sales and support channel” kind of deal so it will be 1 + 1 = 3 accretive for sure.… Read More


Design and Optimization of Analog IP is Possible

Design and Optimization of Analog IP is Possible
by Daniel Payne on 12-04-2015 at 7:00 am

Designing Analog IP is often referred to as a “black art”, something that only highly experienced craftsmen can produce using transistor-level techniques that aren’t shared outside of their closely held group of trusted co-workers. I’d like to suggest that Analog IP can be designed and optimized … Read More


12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers

12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
by Daniel Payne on 10-07-2015 at 7:00 am

My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More


Optimizing SRAM IP for Yield and Reliability

Optimizing SRAM IP for Yield and Reliability
by Daniel Payne on 08-31-2015 at 12:00 pm

My IC design career started out with DRAM at Intel, and included SRAM embedded in GPUs, so I recall some common questions that face memory IP designers even today, like:

  • Does reading a bit flip the stored data?
  • Can I write both 0 and 1 into every cell?
  • Will read access times be met?
  • While lowering the supply voltage does the cell data retain?
Read More