All Things Semiconductor!
Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More
I’ve done SRAM and DRAM design before as a circuit designer from 1978-1986, but in 2016 there are so many more challenges to using 28nm and 14nm on FDSOI technology. One way to keep abreast of SRAM design is to read conference papers, so I just finished a paper from authors at STMicroelectronics and MunEDA presented at the IEEE… Read More
I was born in 1957, the same year that the Soviets launched the first satellite into Earth orbit, officially starting the Space Race between two global super powers. Today there are many countries engaged in space research and I just read about how engineers at IEAv (Institute for Advanced Studies) in Brazil did their IC design optimization… Read More
Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang,… Read More
As I mentioned in “EDA Dead Pool” acquisitions in our industry will continue at a rapid pace. The latest victim is 10 year old French company Infiniscale who was recently purchased by Silvaco. This was more of a “let’s put your product through our massive sales and support channel” kind of deal so it will be 1 + 1 = 3 accretive… Read More
Designing Analog IP is often referred to as a “black art”, something that only highly experienced craftsmen can produce using transistor-level techniques that aren’t shared outside of their closely held group of trusted co-workers. I’d like to suggest that Analog IP can be designed and optimized … Read More
My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More
My IC design career started out with DRAM at Intel, and included SRAM embedded in GPUs, so I recall some common questions that face memory IP designers even today, like:
There are three critical goals that designers of custom digital designs and memories look to achieve with high sigma verification:
(1) obtaining accurate results,
(2) achieving results with good run-time (efficiency), and
(3) gaining proper insight into how their circuit is behaving along with an understanding of failure … Read More
We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low… Read More
Concerned about IP security threats for your SoCs?
Achronix: Accelerate Data Processing Algorithms using FPGAs with 2D Network-on-Chip
PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior
Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation
REPLAY: Avoiding CDM (Charged Device Model) ESD Failures
REPLAY: eFPGA – “What a great idea! But I have no idea how I’d use it!”
REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification
REPLAY: Fabless: The Transformation of the Semiconductor Industry
REPLAY: The Brave New World of Customized Memory
REPLAY: Embedded FPGA: The Fabric for Optimized Machine Learning
REPLAY: VLSI Design Methodology Development
REPLAY: Lightspeed Data Sync – Design Workspace Problems Solved!
REPLAY: Desinging Complex SoCs and Dealing with Multiple File Formats?
REPLAY: How ASIC/SoC Prototyping Solutions Can Help You!
REPLAY: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
REPLAY: Taiwan ESD Workshop Recording
REPLAY: Reduce Risk and Improve Quality of AMS IP’s using AI-Powered Automated Timing Arc Prediction
REPLAY: Text: A Year of Breakfast Bytes by Paul McLellan (Free PDF Version)
REPLAY: Finding Your Way Through Verification
Response to IP’s Growing Impact On Yield And Reliability