The Brazilian Ministry of Science and Technology (MCTIC) has a research unit, Renato Archer Information Technology Center (CTI), and two of their IC engineers presented at the MunEDA User Group meeting this May on the topic of designing Latching Current Limiter (LCL) circuits for space applications with RHBD (radiation-hardened… Read More
Analog Circuit Migration and Optimization
The MunEDA User Group Meeting (MUGM) has been an annual event since 2006, and this year there were some 80 participants from many customers that attended to share their experiences and learn how to get the best EDA tool results. I’ve been able to view the presentations and archived videos, so will share some of the interesting… Read More
Developing the Lowest Power IoT Devices with Russell Mohn
Russell Mohnis the Co-Founder and Director of RF/AMS Design at InPlay Inc. and his team has been using WiCkeD from MunEDA for several years. We thought the rest of the world would like to learn about his experiences.
How did you get started in semiconductors and what brought you to InPlay?
I was initially drawn to analog and mixed-signal… Read More
Webinar: Enhance Productivity with Machine Learning in the Analog Front-End Design Flow
Analog IC designers can spend way too much time and effort re-using old, familiar, manual iteration methods for circuit design, just because that’s the way it’s always been done. Circuit optimization is an EDA approach that can automatically size all the transistors in a cell, by running SPICE simulations across… Read More
Webinar: Post-layout Circuit Sizing Optimization
My IC design career started out with manually sizing transistors to improve performance, while minimizing layout area and power consumption. Fortunately we don’t have to do manual transistor sizing anymore, thanks to EDA tools that are quicker and more accurate than manual methods. MunEDA is an EDA vendor that has developed… Read More
Automating and Optimizing an ADC with Layout Generators
I first got involved with layout generators back in 1982 while at Intel, and about 10% of a GPU was automatically generated using some code that I wrote. It was an easy task for one engineer to complete, because the circuits were digital, and no optimization was required. In an IEEE paper from the 2022 18th International Conference… Read More
Webinar: Simulate Trimming for Circuit Quality of Smart IC Design
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more.
However, more aggressive time-to-market and higher performance… Read More
Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness times have changed, and circuit designers can work smarter … Read More
WEBINAR: Using Design Porting as a Method to Access Foundry Capacity
There have always been good reasons to port designs to new foundries or processes. These reasons have included reusing IP in new projects, moving an entire design to a smaller node to improve PPA, or second sourcing manufacturing. While there can be many potential business motivations for any of the above, in today’s environment… Read More
Numerical Sizing and Tuning Shortens Analog Design Cycles
By any measure analog circuit design is a difficult and complex process. This point is driven home in a recent webinar by MunEDA. Michael Pronath, VP Products and Solutions at MunEDA, lays out why, even with the assistance of simulators, analog circuit sizing and tuning can consume weeks of time in what can potentially be a non-convergent… Read More