WP_Term Object
(
    [term_id] => 57
    [name] => MunEDA
    [slug] => muneda
    [term_group] => 0
    [term_taxonomy_id] => 57
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 27
    [filter] => raw
    [cat_ID] => 57
    [category_count] => 27
    [category_description] => 
    [cat_name] => MunEDA
    [category_nicename] => muneda
    [category_parent] => 157
    [is_post] => 1
)

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying parameters. However, the high number of varying parameters operating on each device in a design creates a huge multidimensional problem.

The baseline approach is to use Monte Carlo, randomly selecting process variables based on the distribution function for each. This brute force approach can require enormous amounts of time and compute resources, so over the years more sophisticated methods have been developed to shorten the process.

MunEDA is a leading provider of solutions for analyzing variability and its effects on circuit operation and yield. They have developed highly effective solutions based on statistical analysis theory that are practical and save time. With the high volumes involved with modern consumer devices, even failures on the order of parts per million are unacceptable. So, it is vitally important that designers have the right tools to perform analysis up to and beyond six-sigma.

MunEDA will be presenting a free live webinar on the topic of Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis on May 8[SUP]th[/SUP] at 10AM PDT, there will also be presentations for the Asia and European time zones, to make viewing convenient.

The webinar will be moderated by MunEDA’s Andreas Ripp, and the presenter will be Dr. Michael Pronath, also from MunEDA. The webinar is intended for full-custom circuit designers, project leaders and managers responsible for design verification and full custom design for yield. They will discuss the pros and cons of a range of techniques to predict circuit yield and robustness. Also, they will highlight the applicability of the techniques to actual circuit design problems.

It will definitely be worthwhile to sign up for this webinar and to lean about this important topic.