WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. … Read More


Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying… Read More


The Intention View: Disruptive Innovation for Analog Design

The Intention View: Disruptive Innovation for Analog Design
by Daniel Nenni on 04-20-2018 at 7:00 am

Intento Design builds responsive analog EDA. The ID-Xplore[SUP]TM[/SUP] tool is used for analog design acceleration and technology porting at the functional level, helping companies move analog IP quickly between technology nodes and across business units. The Intention view[SUP]TM[/SUP] is a simple, elegant, and powerful… Read More


Webinar – Low Power Circuit Sizing for IoT

Webinar – Low Power Circuit Sizing for IoT
by Tom Simon on 05-19-2017 at 7:00 am

Optimizing analog designs has always been a difficult and tricky process. Designing for IoT applications has only made this more difficult with the added importance of minimizing power. Unlike other circuit parameters, it is not easy to specify power as a design goal when using equations. Power is a resultant property and must… Read More


Who knew designing PLL’s was so complicated?

Who knew designing PLL’s was so complicated?
by Tom Simon on 03-27-2017 at 12:00 pm

Well it comes as no surprise to those that use and design them, that PLL’s are a world unto themselves and very complicated indeed. With PLL’s we are talking about analog designs that rely on ring oscillators or LC tanks. They are needed on legacy nodes, like the ones that IoT chips are based on, and they are crucial for high speed advanced… Read More


Tuning Analog IP for High Yield at SMIC

Tuning Analog IP for High Yield at SMIC
by Daniel Payne on 12-29-2015 at 12:00 pm

Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang,… Read More


Managing Design Flows in RF Modules

Managing Design Flows in RF Modules
by Majeed Ahmad on 04-24-2015 at 7:00 pm

The semiconductor industry is expected to grow at a reasonable pace in 2015 and beyond, with the biggest market being compute applications followed by wireless and consumer applications. The highest growth, however, is expected to be in application-specific products for devices such as smartphones, wearables, memories, … Read More


Simple Analog ASIC Solves Thermal Analysis Problems

Simple Analog ASIC Solves Thermal Analysis Problems
by admin on 03-02-2015 at 1:00 pm

Image RemovedIn a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds,… Read More


How to detect weak nodes in a power-off analog circuit?

How to detect weak nodes in a power-off analog circuit?
by Jean-Francois Debroux on 09-01-2014 at 4:00 pm

Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.

When a branch is set in that high impedance… Read More


Digital, Analog, Software, IP – Isn’t it all just the same?

Digital, Analog, Software, IP – Isn’t it all just the same?
by Daniel Payne on 04-25-2014 at 8:31 pm

Designing an SoC requires a team, and the engineers typically use lots of specialized EDA software and semiconductor IP to get the job done. Many have started to ask about how designing a chip is different than designing and managing a large software project, or how is analog design different than digital design in terms of managing… Read More