WP_Term Object
(
    [term_id] => 8
    [name] => ClioSoft
    [slug] => cliosoft
    [term_group] => 0
    [term_taxonomy_id] => 8
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 96
    [filter] => raw
    [cat_ID] => 8
    [category_count] => 96
    [category_description] => 
    [cat_name] => ClioSoft
    [category_nicename] => cliosoft
    [category_parent] => 157
)

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for most design managers, analog designers, and EDA system architects to watch and well worth the time for most layout engineers as well.

I think all in the audience will understand the need for reuse. But we don’t always consider all the ways that reuse can be applied. In its most basic form, it simply means to reuse parts of a design that were already created in a different design project. It is a straightforward concept when we think about major functional blocks or subsystems. The larger the function that is reused, the more likely it may need to be modified for use in a new design. The fact that some modification may be needed is not necessarily bad; it is just a bit of additional effort. Modifying the previous IP may be much more efficient than creating a new solution from scratch.

It is also not simply major functional blocks that can be reused. You may also need to tune analog functions for a given process. Reusable analog IP is highly valued.  For example, a PLL design for use in on design may be easily reused in another design on the same process. While it cannot be directly reused in another process, it may be fine with some small modifications. This is especially valuable if the prior design is in silicon, and real performance data now exists for the block. Of course, the reuse of IP should also extend to all of your foundation IP – standard cell, IO cells, memory instances, PLLs, etc.

Saving all your IP is important. However, you need to be able to find the IP when you need it and also have the information you need to utilize that IP. ClioSoft’s designHUB® was built to make it easier to store, locate, and apply your valuable IP. designHUB® first started shipping in May of 2017 has been successfully deployed in many companies. This webinar goes into more detail on how you can use designHUB® in your design environment.

The primary presenter in the webinar is Karim Khalfan, ClioSoft’s Vice President of the Application Engineering. Karim has led the deployment of ClioSoft’s SOS7 design data and IP management into ClioSoft’s large customer base. He has also written several articles and white papers related to SoC design data management. Karim has a BSCS degree from the University of Texas and holds a patent on defining a universal data management adapter to be used for integration with any EDA tool. As you will see in the webinar, he is can clearly explain this technology.

To access the replay of this webinar, go to this page and click on “View recording.”  This webinar is one of several in this year’s SemiWiki Webinar Series. A list of upcoming webinars, as well as other available replays, can be found in the left column on the SemiWiki homepage.