Cliosoft and Microsoft to Collaborate on the RAMP Program

We have all heard of many advanced technological inventions and products from the defense sector that subsequently got commercialized. While most of the Defense Advanced Research Projects Agency (DARPA) projects are classified secrets, many military innovations have had great influence in the commercial sector in the fields of electronics, communications and computer science. A well-known invention that we all rely on every day, the Internet, had its beginnings from such a project. Since its commercialization, so many advances have happened with and using the Internet including cloud computing.

While the commercial sector has made incredible advances over time, the defense sector has been mostly limited by security concerns and related matters. The Department of Defense (DoD) and the traditional Defense Industrial Base (DIB) are still following obsolete practices and outdated processes in some fields. In particular, as they relate to State-of-the-Art (SOTA) custom IC and System On a Chip (SoC) design and associated physical design. The Navy and Air Force having recognized this, have embarked on an initiative to leverage commercial capabilities to demonstrate secure enhanced design. The initiative is called the Rapid Assured Microelectronics Prototypes (RAMP) program. The purpose of this prototype is to facilitate the rapid development of IC hardware for further evaluation and technology enablement of the DoD. The RAMP program is now in its second phase. Microsoft has been tasked with leading the program by collaborating with companies in the electronics, EDA, semiconductor and related fields.

Microsoft has selected the following industry leaders to collaborate with: Ansys, Applied Materials, Inc., BAE Systems, Battelle Memorial Institute, Cadence Design Systems, Cliosoft, Inc., Flex Logix, GlobalFoundries, Intel Federal, Raytheon Intelligence and Space, Siemens EDA, Synopsys, Inc., Tortuga Logic, and Zero ASIC Corporation.

This article will focus on what Cliosoft brings to the RAMP program.

Cliosoft’s sole focus is helping semiconductor companies manage their design data and their IP.

Its SOS family of design management solutions serves as the backbone for design collaboration at  many of the largest semiconductor companies. Cliosoft also provides an enterprise IP management platform called HUB that is used by companies to easily create, publish and reuse their design IPs. Their Visual Design Diff (VDD) platform allows design teams to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in the design editor. Together, the above three data platforms enable easy and secure handling of data and IP through all aspects of microelectronics development and workflow. Let’s take a closer look.

Designing Flexibility

Design teams need the flexibility to be able to use multi-vendor tool flow on their designs. SOS is integrated and production tested with design tools from multiple vendors. Efficient management of design data and upkeep of proper documentation requires disciplined effort from the team members. Making it easy for them to invoke SOS revision control & design data management features directly from their preferred tools helps achieve success.

Creativity, IP ReUse and Return on Investment

Cliosoft HUB lets people across an enterprise share their IP and expertise with others. It enables problems to be solved quickly by crowdsourcing and designs to be completed faster without reinventing the wheel. Cliosoft HUB helps manage and track these collaborative efforts.

Effective IP reuse requires an IP-based design methodology and a good software infrastructure to enable it. It also requires an easy way for designers to find the right IP and gauge its quality. When reusing an IP, designers need the ability to get help with the IP if needed, report issues found, and be notified if there are updates. Cliosoft HUB addresses all of these requirements.

Engineers needing a piece of IP may find that it has already been developed in another division. They can now quickly access the IP and leverage the expertise of the IP creators. They can also benefit from other users in the enterprise who may have integrated that IP into their designs. All the interaction is recorded within Cliosoft HUB and becomes a knowledge base that future users of the IP can leverage.

IP Assembly

For situations when a piece of higher-level IP must be developed internally, it is usually a matter of assembly using lower-level IP blocks. In order to successfully complete this assembly process, hierarchical visibility is required along with access to the knowledge base and issues tracking of all IP blocks.

IP Traceability

Traceability is key to understanding the evolution of an IP block, and the modifications that were made for bug fixes or new features. Cliosoft HUB provides IP traceability through a knowledge base that describes the evolution, reuse and integration of IP into various products. This kind of traceability is especially required for compliance reasons in the defense sector, automotive and medical device markets. Standards such as ISO26262 and MIL-STD-882 mandate this kind of documentation. All of Cliosoft’s products are ISO26262 certified.

Also Read

DAC 2021 – Cliosoft Overview

Cliosoft Webinar: What’s Needed for Next Generation IP-Based Digital Design

Webinar – Why Keeping Track of IP in the Enterprise Really Matters