DesignCon 2016 — signal integrity must be power-aware!

DesignCon 2016 — signal integrity must be power-aware!
by Tom Dillinger on 01-31-2016 at 6:00 pm

DesignCon is a unique conference — its tagline is “Where the Chip meets the Board”. Held each January in Santa Clara, the conference showcases a wealth of new technologies for advanced packaging, printed circuit board fabrication, connectors, cables, and related analysis equipment (e.g, BERT, VNA, scopes). Of specific… Read More


Importance of Data Management in SoC Verification

Importance of Data Management in SoC Verification
by Pawan Fangaria on 04-22-2014 at 6:00 am

In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent… Read More


Analog ECOs and Design Reviews: How to Do Them Better

Analog ECOs and Design Reviews: How to Do Them Better
by Paul McLellan on 09-02-2013 at 1:00 am

One of the challenges in doing a complex analog or mixed signal design is that things get out of step. One designer is tweaking the schematic and re-simulating, another is tweaking the layout of transistors, another is changing the routing. This is not because the design flow is messed up, but rather it reflects reality. If you wait… Read More


ClioSoft Update 2012!

ClioSoft Update 2012!
by Daniel Nenni on 05-30-2012 at 8:05 pm


ClioSoft had a record year in 2011, right after they started working with SemiWiki. Coincidence? Of course not. You can visit the SemiWiki ClioSoft landing page HERE. Be sure and read the customer interviews done by Daniel Payne. It is really nice to see customers stand up and speak for their tools, much more interesting than listening… Read More


Hardware Configuration Management at DAC

Hardware Configuration Management at DAC
by Daniel Payne on 06-17-2011 at 6:20 pm

Intro
Show me what has changed in my RTL or Schematic since the last time I looked. This task is now automated by Cliosoft with their new hierarchical tool called Visual Design Difference (VDD). Srinath showed me what was new for DAC.


Srinath Anantharaman

Notes
LSI, STMicro – use DesignSync for their DM but use VDD for seeing visual… Read More