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DesignCon 2016 — signal integrity must be power-aware!

DesignCon 2016 — signal integrity must be power-aware!
by Tom Dillinger on 01-31-2016 at 6:00 pm

DesignCon is a unique conference — its tagline is “Where the Chip meets the Board”. Held each January in Santa Clara, the conference showcases a wealth of new technologies for advanced packaging, printed circuit board fabrication, connectors, cables, and related analysis equipment (e.g, BERT, VNA, scopes). Of specific interest are the presentations and EXPO floor demonstrations from the EDA vendors focused on design and analysis tools for very complex packages and boards.
There were several key takeaways from this year’s DesignCon:

  • DDR4 interfacing is significantly more complex than DDR3.

This single-ended parallel interface will require a detailed signal integrity analysis methodology comparable to a SerDes design, due to the data rates, asymmetric voltage levels/transitions, and unique impedance profiles associated with different combinations of active memory banks.

  • The DDR4 data bus inversion (DBI) feature adds to the analysis complexity and interface standard compliance verification

Successive parallel data bus transitions are optimized by transmitting true or inverted data (with the DBI signal), to minimize simultaneous switching output (SSO) noise.

And, perhaps most significantly,

  • Power-aware models will be required for signal integrity analysis of future high-speed interfaces.

The impact of the power distribution network (PDN) noise on signal behavior has increased, due to higher data rates and smaller signal swings, and thus reduced noise and timing margins. The figure below shows a typical time-dependent power supply fluctuation at the controller and DIMM sides of a DDR4 interface design (DQ signals). Specifically, the extracted models for active circuitry used in SI analysis will require additional power supply-dependent detail, as represented using features of the new IBIS 5.0 standard — more on that shortly.

At the conference, Zhen Mu, Senior Principal Product Engineer at Cadence, presented the paper “Block-Level Modeling-Based Power and Signal Integrity Performance Optimization of Integrated Core and Memory System”, describing a methodology for power-aware parallel bus signal integrity analysis, utilizing key features in the Sigrity SystemSI platform.

The key concept is highlighted in the following figure.


The chip-level power-aware models are divided into core and I/O domains, or “blocks” in the SystemSI nomenclature.

The PDN model for the core is extracted separately using the Sigrity PowerSI tool, as the core supply injects noise into the overall system but does not directly impact the I/O behavior. The package and PCB supply VDD and GND plane references are used. The core model will ultimately include full PDN detail, out to the Voltage Reference Module (VRM) providing regulation to the VDD supply.

A detailed power-aware signal integrity model for the parallel bus signals is extracted as a separate block, using the VDD_IO supply and GND plane references (out to the VDD_IO VRM, as well).

The core PDN and the I/O signal models are then connected at the appropriate ports, and merged with models for the package and PCB to create the fully integrated power-aware model, as illustrated below.


A combination of tools is used for individual block and full system model generation. Sigrity SystemSI is the overall platform used to represent the full model hierarchy and port connections, utilizing the Cadence Model Connection Protocol (MCP) mapping representation to reduce the port data volume. Sigrity XcitePI extracts the on-chip PDN and I/O nets from layout data, including power and signal net RLC parasitic detail. As mentioned above, Sigrity PowerSI generates the package and PCB models, including coupling between signal and power nets, with a true return current path reflected in the model.

A unique application derives the parallel I/O bus model, with its associated power-dependent behavior — Sigrity T2B. Transistor-to-Behavioral model conversion (T2B) is the crucial utility needed to add the influence of the I/O PDN on the bus signal circuits. From the detailed chip electrical parasitic model, T2B generates the IBIS 5.0 representation, suitable for advanced signal integrity analysis.

IBIS 5.0 represents a significant leap in driver/receiver electrical modeling, well beyond the traditional “simple impedance” abstract. It includes power/ground current detail — e.g., drive current, crowbar switching current, on-die decap currents. This representation is a “must have” to enable suitable power-aware signal integrity analysis, to enable the impact of the supply fluctuations to be incorporated into the results.

During initial design implementation, optimizations are enabled in the SystemSI environment by repeating the signal integrity analysis with a sweep of PDN parameters, such as the on-die decoupling capacitors.

A major theme of this year’s DesignCon was that high-speed interface signal integrity analysis requires the full detail associated with a power-aware model. The simplifying assumption of doing SI analysis with “pure” supply references will no longer suffice. The Cadence Sigrity SystemSI power-aware methodology addresses this requirement — more information about SystemSI is available here.

-chipguy


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