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Useful Skew in Production Flows

Useful Skew in Production Flows
by Tom Dillinger on 12-13-2019 at 6:00 am
Categories: EDA, Synopsys

The concept of applying useful clock skew to the design of synchronous systems is not new.  To date, the application of this design technique has been somewhat limited, as the related methodologies have been rather ad hoc, to be discussed shortly.  More recently, the ability to leverage useful skew has seen a major improvement,… Read More

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Characteristics of an Efficient Inference Processor

Characteristics of an Efficient Inference Processor
by Tom Dillinger on 12-11-2019 at 10:00 am
Categories: eFPGA, Flex Logix

The market opportunities for machine learning hardware are becoming more succinct, with the following (rather broad) categories emerging:

  1. Model training:  models are evaluated at the “hyperscale” data center;  utilizing either general purpose processors or specialized hardware, with typical numeric precision of 32-bit
… Read More
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Package Reliability Issues Cost Money

Package Reliability Issues Cost Money
by Tom Dillinger on 11-13-2019 at 6:00 am
Categories: ANSYS, Inc., EDA

Advanced packaging technology is enabling “More Than Moore” scaling of heterogeneous technology die.  At the recent EDPS Symposium in Milpitas, Craig Hillman, Director of Product Development, DfR Solutions, at ANSYS gave a compelling presentation, “Reliability Challenges in Advanced Packaging”.  The key takeaway messages… Read More

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5G Deployments – The Analysis Requirements are Ginormous

5G Deployments – The Analysis Requirements are Ginormous
by Tom Dillinger on 10-07-2019 at 10:00 am
Categories: 5G, ANSYS, Inc., EDA
1 Comment

The introduction of 5G communications support offers tremendous potential across a broad spectrum of applications (no pun intended).  5G is indeed quite encompassing, across a wide range of frequencies – the figure below illustrates the common terminology used, from low-band, mid-band (“sub 6G”), and high-band (“mmWave… Read More

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High-Speed PHY IP for Hyperscale Data Centers

High-Speed PHY IP for Hyperscale Data Centers
by Tom Dillinger on 09-25-2019 at 10:00 am
Categories: EDA, Synopsys
4 Comments

A new designation has recently entered the vernacular of the computing industry – a hyperscale data center.  The adjective hyperscale implies the ability of a computing resource to scale corresponding to increased workload, to maintain an appropriate quality of service.

The traditional enterprise data center is often characterized… Read More

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AI Inference at the Edge – Architecture and Design

AI Inference at the Edge – Architecture and Design
by Tom Dillinger on 09-23-2019 at 10:00 am
Categories: eFPGA, Flex Logix, IP

In the old days, product architects would throw a functional block diagram “over the wall” to the design team, who would plan the physical implementation, analyze the timing of estimated critical paths, and forecast the signal switching activity on representative benchmarks.  A common reply back to the architects was, “We’… Read More

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Webinar: VLSI Design Methodology Development (new text)

Webinar: VLSI Design Methodology Development (new text)
by Tom Dillinger on 08-28-2019 at 10:00 am
Categories: Events
1 Comment

Daniel Nenni was gracious enough to encourage me to conduct a brief webinar describing a new reference text, recently published by Prentice-Hall, part of the Semiwiki Webinar Series.

VLSI DESIGN Methodology Development Webiner Replay

Background

I was motivated to write the text to provide college students with a broad background… Read More

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The Coming Tsunami in Multi-chip Packaging

The Coming Tsunami in Multi-chip Packaging
by Tom Dillinger on 07-12-2019 at 6:00 am
Categories: Foundries, Intel
6 Comments

The pace of Moore’s Law scaling for monolithic integrated circuit density has abated, due to a combination of fundamental technical challenges and financial considerations.  Yet, from an architectural perspective, the diversity in end product requirements continues to grow.  New heterogeneous processing units are being… Read More

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SiP is the new SoC @ 56thDAC

SiP is the new SoC @ 56thDAC
by Tom Dillinger on 06-19-2019 at 6:48 pm
Categories: Cadence, EDA, Events
3 Comments

The emergence of 3D packaging technology has been accompanied by the term “more than Moore”, to reflect the increase in areal circuit density at a rate that exceeds the traditional IC scaling pace associated with Moore’s Law.  At the recent Design Automation Conference in Las Vegas, numerous exhibits on the vendor floor presented… Read More

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An Update from Joe Sawicki @ Mentor, a Siemens Business 56thDAC

An Update from Joe Sawicki @ Mentor, a Siemens Business 56thDAC
by Tom Dillinger on 06-17-2019 at 10:22 pm
Categories: Mentor, a Siemens Business

Executives from the major EDA companies attend the Design Automation Conference to introduce new product features, describe new initiatives and collaborations, meet with customers, and participate in lively conference panel discussions.  Daniel Nenni and I were fortunate to be able to meet with Joe Sawicki, Executive Vice… Read More