Highlights of the TSMC Technology Symposium – Part 3

Highlights of the TSMC Technology Symposium – Part 3
by Tom Dillinger on 09-09-2020 at 8:00 am

CoWoS features

Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time.  This article is the last of three that attempts to summarize the highlights of the presentations.  This article focuses on the technology design enablement roadmap, as described by Cliff Hou, SVP, R&D.

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Highlights of the TSMC Technology Symposium – Part 2

Highlights of the TSMC Technology Symposium – Part 2
by Tom Dillinger on 09-07-2020 at 8:00 am

3D Fabric

Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time.  This article is the second of three that attempts to summarize the highlights of the presentations.  This article focuses on the TSMC advanced packaging technology roadmap, as described by Doug Yu, VP, R&D.

KeyRead More


Highlights of the TSMC Technology Symposium – Part 1

Highlights of the TSMC Technology Symposium – Part 1
by Tom Dillinger on 09-04-2020 at 8:00 am

A72 core high density

Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time.  This article is the first of three that attempts to summarize the highlights of the presentations.

This article focuses on the TSMC process technology roadmap, as described by the following executives:

  • Y.J. Mii, SVP,
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A “Super” Technology Mid-life Kicker for Intel

A “Super” Technology Mid-life Kicker for Intel
by Tom Dillinger on 08-17-2020 at 10:00 am

TigerLake WillowCove

Summary
At the recent Intel Architecture Day 2020 symposium, a number of technology enhancements to the Intel 10nm process node were introduced.  The cumulative effect of these enhancements would provide designs with a performance boost (at iso-power) approaching 20% – a significant intra-node enhancement, to be sure.  The… Read More


Thermo-compression bonding for Large Stacked HBM Die

Thermo-compression bonding for Large Stacked HBM Die
by Tom Dillinger on 07-24-2020 at 8:00 am

HMB stack

Summary

Thermo-compression bonding is used in heterogeneous 3D packaging technology – this attach method was applied to the assembly of large (12-stack and 16-stack) high bandwidth memory (HBM) die, with significant bandwidth and power improvements over traditional microbump attach.

Introduction

The rapid growth of heterogeneous… Read More


In-Memory Computing for Low-Power Neural Network Inference

In-Memory Computing for Low-Power Neural Network Inference
by Tom Dillinger on 07-17-2020 at 10:00 am

von Neumann bottleneck

“AI is the new electricity.”, according to Andrew Ng, Professor at Stanford University.  The potential applications for machine learning classification are vast.  Yet, current ML inference techniques are limited by the high power dissipation associated with traditional architectures.  The figure below highlights the … Read More


A Compelling Application for AI in Semiconductor Manufacturing

A Compelling Application for AI in Semiconductor Manufacturing
by Tom Dillinger on 07-06-2020 at 6:00 am

AI opportunities

There have been a multitude of announcements recently relative to the incorporation of machine learning (ML) methods into EDA tool algorithms, mostly in the physical implementation flows.  For example, deterministic ML-based decision algorithms applied to cell placement and signal interconnect routing promise to expedite… Read More


Contact over Active Gate Process Requirements for 5G

Contact over Active Gate Process Requirements for 5G
by Tom Dillinger on 07-01-2020 at 6:00 am

frequency 5G

Summary
A recent process enhancement in advanced nodes is to support the fabrication of contacts directly on the active gate area of a device.  At the recent VLSI 2020 Symposium, the critical advantages of this capability were highlighted, specifically in the context of the behavior of RF CMOS devices needed for 5G designs.

IntroductionRead More


Optimizing Chiplet-to-Chiplet Communications

Optimizing Chiplet-to-Chiplet Communications
by Tom Dillinger on 06-29-2020 at 6:00 am

bump dimensions

Summary
The growing significance of ultra-short reach (USR) interfaces on 2.5D packaging technology has led to a variety of electrical definitions and circuit implementations.  TSMC recently presented the approach adopted by their IP development team, for a parallel-bus, clock-forwarded USR interface to optimize power/performance/area… Read More


Multi-Vt Device Offerings for Advanced Process Nodes

Multi-Vt Device Offerings for Advanced Process Nodes
by Tom Dillinger on 06-26-2020 at 6:00 am

Ion Ioff

Summary
As a result of extensive focus on the development of workfunction metal (WFM) deposition, lithography, and removal, both FinFET and gate-all-around (GAA) devices will offer a wide range of Vt levels for advanced process nodes below 7nm.

Introduction
Cell library and IP designers rely on the availability of nFET and pFET… Read More