The Latest in Dielectrics for Advanced Process Nodes

The Latest in Dielectrics for Advanced Process Nodes
by Tom Dillinger on 01-12-2021 at 6:00 am

new ILDs v2

Of the three types of materials used in microelectronics – i.e., semiconductors, metals, and dielectrics – the first two often get the most attention.  Yet, there is a pressing need for a rich variety of dielectric materials in device fabrication and interconnect isolation to satisfy the performance, power, and reliability … Read More


Technology Optimization for Magnetoresistive RAM (STT-MRAM)

Technology Optimization for Magnetoresistive RAM (STT-MRAM)
by Tom Dillinger on 01-06-2021 at 6:00 am

profile simulations

Spin-transfer torque magnetoresistive RAM (STT-MRAM) has emerged from several foundries as a very attractive IP option.  An introduction to MRAM technology from GLOBALFOUNDRIES was provided in this earlier SemiWiki article. [1]

Briefly, STT-MRAM is a non-volatile storage option with the following attractive characteristics… Read More


Optimization for pFET Nanosheet Devices

Optimization for pFET Nanosheet Devices
by Tom Dillinger on 01-04-2021 at 6:00 am

Intel flow TEM

The next transition from current FinFET devices at advanced process nodes is the “nanosheet” device, as depicted in the figure below. [1]

The FinFET provides improved gate-to-channel electrostatic control compared to a planar device, where the gate traverses three sides of the fin.  The “gate-all-around” characteristics… Read More


What Might the “1nm Node” Look Like?

What Might the “1nm Node” Look Like?
by Tom Dillinger on 12-28-2020 at 6:00 am

transistor density

The device roadmap for the next few advanced process nodes seems relatively clear.  The FinFET topology will subsequently be displaced by a “gate-all-around” device, typically using multiple stacked channels with a metal gate completely surrounding the “nanosheets”.  Whereas the fin demonstrates improved gate-to-channel… Read More


A Research Update on Carbon Nanotube Fabrication

A Research Update on Carbon Nanotube Fabrication
by Tom Dillinger on 12-22-2020 at 10:00 am

IV measurement testchip

It is quite amazing that silicon-based devices have been the foundation of our industry for over 60 years, as it was clear that the initial germanium-based devices would be difficult to integrate at a larger scale.  (GaAs devices have also developed a unique microelectronics market segment.)  More recently, it is also rather … Read More


3DIC Design, Implementation, and (especially) Test

3DIC Design, Implementation, and (especially) Test
by Tom Dillinger on 12-20-2020 at 8:00 am

IO cell

The introduction of direct die-to-die bonding technology into high volume production has the potential to substantially affect the evolution of the microelectronics industry.  The concerns relative to the “end of Moore’s Law”, the diminishing returns of continued (monolithic) CMOS process scaling, and the disruptive effect… Read More


Advanced Process Development is Much More than just Litho

Advanced Process Development is Much More than just Litho
by Tom Dillinger on 12-16-2020 at 10:00 am

Vt distribution

The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates.  The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area.  Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy… Read More


Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am

LVS flow phases

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint.  Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all… Read More


A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


Highlights of the TSMC Technology Symposium – Part 3

Highlights of the TSMC Technology Symposium – Part 3
by Tom Dillinger on 09-09-2020 at 8:00 am

CoWoS features

Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time.  This article is the last of three that attempts to summarize the highlights of the presentations.  This article focuses on the technology design enablement roadmap, as described by Cliff Hou, SVP, R&D.

Key TakeawaysRead More