AI at the Edge

AI at the Edge
by Tom Dillinger on 12-20-2018 at 7:00 am

Frequent Semiwiki readers are well aware of the industry momentum behind machine learning applications. New opportunities are emerging at a rapid pace. High-level programming language semantics and compilers to capture and simulate neural network models have been developed to enhance developer productivity (link). Researchers… Read More


Architecture for Machine Learning Applications at the Edge

Architecture for Machine Learning Applications at the Edge
by Tom Dillinger on 10-31-2018 at 2:01 pm

Machine learning applications in data centers (or “the cloud”) have pervasively changed our environment. Advances in speech recognition and natural language understanding have enabled personal assistants to augment our daily lifestyle. Image classification and object recognition techniques enrich our social media experience,… Read More


The Latest from Samsung Semiconductor

The Latest from Samsung Semiconductor
by Tom Dillinger on 10-29-2018 at 12:00 pm

Earlier this Spring, Samsung Foundry held a technology forum, describing their process roadmap and supporting ecosystem developments (link). Recently, the larger Samsung Semiconductor organization conducted a Tech Day at their campus in San Jose, presenting (and demo-ing) a broader set of products. The focus of the day was… Read More


IBIS-AMI Model Generation Simplified

IBIS-AMI Model Generation Simplified
by Tom Dillinger on 10-25-2018 at 12:00 pm

The increasing demand for data communication throughput between system components has driven the requirement for faster SerDes IP data rates. The complexity of the transmit (Tx) and receive (Rx) signal conditioning functions has correspondingly evolved. As a result, the simulation methodology for SerDes electrical interface… Read More


The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More


Advanced Materials and New Architectures for AI Applications

Advanced Materials and New Architectures for AI Applications
by Tom Dillinger on 10-17-2018 at 7:00 am

Over the past 50 years in our industry, there have been three invariant principles:

  • Moore’s Law drives the pace of Si technology scaling
  • system memory utilizes MOS devices (for SRAM and DRAM)
  • computation relies upon the “von Neumann” architecture

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Avionics and Embedded FPGA IP

Avionics and Embedded FPGA IP
by Tom Dillinger on 10-15-2018 at 12:00 pm

The design of electronic systems for aerospace applications shares many of the same constraints as apply to consumer products – e.g., cost (including NRE), power dissipation, size, time-to-market. Both market segments are driven to leverage the integration benefits of process scaling. … Read More


Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum

Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum
by Tom Dillinger on 10-09-2018 at 7:00 am

Each year, TSMC hosts two major events for customers – the Technology Symposium in the spring, and the Open Innovation Platform Ecosystem Forum in the fall. The Technology Symposium provides updates from TSMC on:
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Neural Network Efficiency with Embedded FPGA’s

Neural Network Efficiency with Embedded FPGA’s
by Tom Dillinger on 09-21-2018 at 12:00 pm

The traditional metrics for evaluating IP are performance, power, and area, commonly abbreviated as PPA. Viewed independently, PPA measures can be difficult to assess. As an example, design constraints that are purely based on performance, without concern for the associated power dissipation and circuit area, are increasingly… Read More


Analytics and Visualization for Big Data Chip Analysis

Analytics and Visualization for Big Data Chip Analysis
by Tom Dillinger on 08-28-2018 at 12:00 pm

Designers require comprehensive logical, physical, and electrical models to interpret the results of full-chip power noise and electromigration analysis flows, and subsequently deduce the appropriate design updates to address any analysis issues. These models include: LEF, DEF, Liberty library models (including detailed… Read More