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TSMC Arizona Fab Cost Revisited

TSMC Arizona Fab Cost Revisited
by Scotten Jones on 10-13-2021 at 8:00 am

TSMC North America Fabs

Back in May of 2020 I published some comparisons of the cost to run a TSMC fab in Arizona versus their fabs in Taiwan. I found the fab operating cost based on the country-to-country difference to only be 3.4% higher in the US and then I found an additional 3.8% because of the smaller fab scale. Since that time, I have continued to encounter… Read More


Intel Accelerated

Intel Accelerated
by Scotten Jones on 07-27-2021 at 6:00 am

Intel Process Name Decoder

Intel presented yesterday on their plans for process technology and packaging over the next several years. This was the most detailed roadmap Intel has ever laid out. In this write up I will analyze Intel’s process announcement and how they match up with their competitors.

10nm Super Fin (SF)

10nm is now in volume production in three… Read More


VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials

VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials
by Scotten Jones on 07-19-2021 at 6:00 am

T8 1 Arjun Page 08

At the 2021 VLSI Technology Symposium, Imec presented on Ruthenium (Ru) and Molybdenum (Mo) as alternate Word Line (WL) materials for 3D NAND Flash “First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D NAND Memory Devices”. I had an opportunity to interview one of the authors: Maarten Rosmeulen.… Read More


VLSI Technology Symposium – Imec Forksheet

VLSI Technology Symposium – Imec Forksheet
by Scotten Jones on 07-06-2021 at 6:00 am

VLSI2021 T2 1 Mertens v2 Page 05

FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.

At the … Read More


VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
by Scotten Jones on 07-02-2021 at 6:00 am

Figure 1

At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More


Is IBM’s 2nm Announcement Actually a 2nm Node?

Is IBM’s 2nm Announcement Actually a 2nm Node?
by Scotten Jones on 05-09-2021 at 6:00 am

Slide1

IBM has announced the development of a 2nm process.

IBM Announcement

What was announced:

  • “2nm”
  • 50 billion transistors in a “thumbnail” sized area later disclosed to be 150mm2 = 333 million transistors per millimeter (MTx/mm2).
  • 44nm Contacted Poly Pitch (CPP) with 12nm gate length.
  • Gate All Around (GAA), there are several ways
Read More

Ireland – A Model for the US on Technology

Ireland – A Model for the US on Technology
by Scotten Jones on 05-02-2021 at 6:00 am

Slide1 2

After I published a recent article about Intel, I was contacted by the Irish Development Agency (IDA) where Intel has a large fab presence and asked if I would like to interview them about the Intel site. The interview with Turlough McCormack of the IDA, started with Intel’s presence in Ireland but then went on to paint an interesting… Read More


How to Spend $100 Billion Dollars in Three Years

How to Spend $100 Billion Dollars in Three Years
by Scotten Jones on 04-25-2021 at 6:00 am

Slide1 1

TSMC recently announced plans to spend $100 billion dollars over three years on capital. For 2021 they announced $30B in total capital with 80% on advanced nodes (7nm and smaller), 10% on packaging and masks and 10% on “specialty”.

If we take a guess at the capital for each year, we can project something like $30B for 2021 (announced),… Read More


SPIE 2021 – Applied Materials – DRAM Scaling

SPIE 2021 – Applied Materials – DRAM Scaling
by Scotten Jones on 04-08-2021 at 10:00 am

Slide1

At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed.

I also spoke to Regina Freed last… Read More


Kioxia and Western Digital and the current Kioxia IPO/Sale rumors

Kioxia and Western Digital and the current Kioxia IPO/Sale rumors
by Scotten Jones on 04-06-2021 at 10:00 am

Slide2

There are a lot of articles out right now discussing a possible IPO for Kioxia or sale of the company with Western Digital (WD) and Micron Technology (MT) mentioned as possible acquirers. Kioxia and WD have a partnership for Flash Memory and on March 18th WD gave a presentation on the state of their partnership and what they see as their… Read More