The slogan for the DesignCon conference has been “where the chip meets the board”. Traditionally, the conference has provided a breadth of technical presentations covering the design and analysis of high-speed communication interfaces and power integrity evaluations between chip, board, and system.
The recent DesignCon event at the Santa Clara Convention Center conveyed a noticeably different theme. The emergence of 2.5D and 3D advanced packaging has necessitated the development of new tools and techniques for the extraction and channel simulation of the disparate interface topologies provided with these packages.
New classes of design requirements have emerged. Whereas interfaces were typically denoted as long reach (LR), medium reach (MR), or short reach (SR), designers are now addressing the unique electrical requirements associated with very short reach (VSR), extra short reach (XSR), and ultra short reach (USR) connections. Each of these interface types have stringent allowable signal loss and crosstalk constraints, at ever higher transmission frequencies.
In addition to the growing diversity of interface types, there is a growing demand for quick turnaround time for design and analysis iterations, while concurrently managing the increasing physical data volume. The interconnect density available on these advanced packages combined with the options for (clock-forwarded) parallel and (NRZ, PAM) serial data transmission requires extensive focus on initial package route planning. The need for a “shift left” approach to advanced packaging design closure needs fast analysis evaluation throughput.
At DesignCon, Feng Ling, CEO of Xpeedic Technology Inc., gave an insightful presentation entitled “High-Performance EM Simulation Solution for Advanced Packaging”. He highlighted how their advanced packaging analysis platform development is addressing these capacity, accuracy, and throughput challenges.
To frame the problem, Feng used the figure below to illustrate the range of physical dimensions which the electromagnetic solver must encompass.
Examples of the types of elements in a 2.5D model to be extracted are shown below, from extremely dense parallel wires associated with HBM die stack signals to embedded routes in a 2.5D interposer to through silicon vias (TSVs) and package substrate traces.
Feng focused on three key features of the Xpeedic Metis EM extraction approach:
- support for data input formats that encompass the disparity, in die, interposer, and package substrate design representations
- an optimal coupling of boundary element method (BEM, aka “method of moments”, for linear piecewise-isotropic materials) and finite element method (FEM) solution algorithms for different domains
- an optimized meshing strategy of the advanced packaging material properties and geometries – e.g., a combined rectangular and triangular surface decomposition
The figures below highlight these features:
To illustrate the efficiency and accuracy of the Metis EM solver, Feng presented comparisons of the computational resources and the insertion loss plus return loss versus frequency results for several advanced package elements (against a reference tool).
An example of these comparisons is illustrated below, for the case of an HBM channel on a 2.5D package:
- CoWoS-R package from TSMC, with an organic interposer
- co-planar signals in the channel in an interspersed supply-signal (GSGSG) configuration
- 2um signal width with 3um spacing
Representative return loss (S-parameter S11) and crosstalk (S13) curves for Metis versus a reference tool are shown, along with the computational resources required.
Specifically, the Metis solver evaluation time efficiencies support the need for fast “pathfinding” design and analysis iterations, to achieve an optimal physical implementation that confirms signal loss budgets are met.
Advanced package design technology has enabled a diverse set of electrical interfaces to be integrated, with high interconnect density provided over short distances. The target frequency of the data rates across these interfaces and the tight signal losses allowed necessitate accurate EM analysis. The design complexity of these packages means that tools must support large dataset size and simultaneously provide fast analysis throughput for signal and power implementation planning. The Metis extraction solution from Xpeedic addresses these requirements.
For more information on Xpeedic Metis, please follow this link.
PS. Perhaps DesignCon could update their slogan, “where heterogeneous chips integrated on an advanced package meets the board”.
Share this post via: