Digital designers have used diff tools for years on their text-based HDL source code, but what about for the transistor-level IC designer, where is their diff tool for schematics or layout?
It turns out that ClioSoft created a visual diff tool aptly named Visual Design Diff and for fun they held a contest to see who could identify the four changes made to the following schematic:
Now draw your attention to the follow modified schematic:
Their interactive game had over 300 contestants give it a try. The winner was DI Stefan Lukas, Manager Design Applicaitn Engineering Graz, Infineon Technologies Austria AG. Stefan won an iPad, then decided instead to donate the prize amount to his favorite charity.
In case you are going crazy trying to find the four differences, here is the answer:
LVS tools are a text-only method to point out differences between schematic netlists and now you have a visual tool to consider adding to your transistor-level IC design flow, called VDD. I can see that this kind of tool would save you many hours of frustrating manual debug in quickly finding what has changed on a schematic over time.
About UsClioSoft was launched in 1997 as a self-funded company, with the SOS design collaboration platform as its first product. The objective was to help manage front end flows for SoC designs. The SOS platform was later extended to incorporate analog and mixed-signal design flows wherever Cadence Virtuoso® was predominantly used. SOS is currently integrated with tools from Cadence®, Synopsys®, Mentor Graphics® and Keysight Technologies®. ClioSoft also provides an enterprise IP management platform for design companies to easily create, publish and reuse their design IPs.
Also ReadShare this post via: