According to the ESD Alliance, the single biggest revenue category in our industry is for semiconductor IP, so the concept of IP reuse is firmly established as a way to get complex products to market more quickly and reducing risk. On the flip side, with hundreds or even thousands of IP blocks in a complex SoC, how does a team, division or corporation know where all of their commercial and internal IP is being used, and what versions should be used? This brings up the whole topic of digital design management.
I did visit Cliosoft at DAC in San Francisco back in December and blogged about it, so I have been familiar with their general approach to digital design management. Recently I viewed their latest webinar on demand, IP-based Digital Design Management that Goes Beyond the Basics.
If you’re new to the concepts of digital design management, then the first section of the webinar is a great place to learn about how files are managed, versioning control and labeling releases. The digital design flow has many steps, EDA tools, IP blocks, and a variety of engineers with specific duties, so orchestrating this complex process requires a more structured approach.
In the webinar you will learn how each of the personas on your team will use a methodology to handle the IP Bill of Materials (BOM). specifications, memory maps, documentation, forums and information sharing. Since IP reuse is a major tenet, you need to have a way to quickly search and find the exact IP required for new projects. Having both internal IP and commercial IP in a catalog makes the search more efficient at the start of a new project.
Working across geographies is important, especially in larger companies, so you’ll need a way to define where each part of an SoC is going to be defined and managed. Knowing the bug fix history for each IP block is essential to getting the correct behavior when using an IP instance. Having two versions of the same IP block should be quickly flagged, because in most cases you really want a single version for each IP on the same SoC.
The tasks of verification engineers are discussed, and tips on how to minimize the storage of EDA tool results presented.
Controlling who has access to all of the IP and at what levels (read, write, geography) was presented for enforcing methodology and meeting legal requirements. Automotive (ISO 26262), defense and aerospace design teams need to know exactly where each IP block has been used for ITAR (International Traffic in Arms Regulations) compliance.
They even included a checklist for teams that are considering which digital design management system to use for their complex projects, that way you know what to look for during an evaluation to compare different vendor approaches.
Cliosoft has a long history in supporting digital design management requirements with tools and a methodology to help ensure compliance and receive automation benefits. IP reuse is the leading methodology for SoC projects today, so having a way to use IP more effectively is a competitive advantage for systems companies.
View the Cliosoft webinar on demand online, it’s 26 minutes long and requires a brief registration.
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