WP_Term Object
(
    [term_id] => 8
    [name] => ClioSoft
    [slug] => cliosoft
    [term_group] => 0
    [term_taxonomy_id] => 8
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 95
    [filter] => raw
    [cat_ID] => 8
    [category_count] => 95
    [category_description] => 
    [cat_name] => ClioSoft
    [category_nicename] => cliosoft
    [category_parent] => 157
)

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. SemiWiki will hold this webinar featuring ClioSoft on Tuesday, September 24, 2019, from 10:00 am to 10:45 am. You can reserve your space here with your work email address.

Over the past decade, the importance of design reuse has become not simply more important, but a mandatory requirement. You cannot design today’s chips, with their tremendous transistor counts, from scratch. There is not enough time. The lack of time to design from scratch is even more clear when we look at analog design. If you have a piece of analog functionality already working in a certain process, you should never redesign it without a very good reason; otherwise, you are simply wasting time and resources. It is not free to move analog IP between process nodes, but it is usually better than “reinventing the wheel.” So, if you are going to look for reusable IP inside your company, where do you start?

ClioSoft announced designHUB® in May 2017. It made its debut at DAC a month later. Since then, many companies have adopted designHUB to reuse their internal and licensed third-party IPs. With ClioSoft’s integration with so many EDA vendors, the adoption of designHUB has been increasing dramatically. This webinar will focus on using designHUB for analog design with Cadence’s Virtuoso.

Sourcing IP can be a time-consuming part of the design process. There is a point at which, if you have not selected the IP you are going to use for a specific function, the design process halts. When selecting IP, there are many things to consider:

  • Basic functionality – What does this IP do?
  • Specifications – In which process was it used? How fast is it? How big is it? How much power does it consume?
  • Features – Does this IP support all the features you need?
  • Usage – How often has it been used? In what types of designs?
  • Cost – Especially in the case of a previously licensed IP, it may not be free
  • Quality – You need to know the previous usage of the IP, and how well it has performed
  • Support – Is there an in-house expert who has used this product that can answer your questions? How do you learn about fixes and workarounds?

Managing and sharing all this information across your company is what designHUB provides. You enable your design community to crowdsource their IP using search mechanisms. You can also set up workflows for addressing the permissions necessary to utilize a given IP. Each design may now more easily share their IP with the rest of the company design community, improving design quality, and reducing design costs.

The webinar will be moderated by Dan Nenni,  Founder of SemiWiki. The presenter will be Karim Khalfan, Vice President of the Application Engineering group at ClioSoft. Karim has led the deployment of ClioSoft’s SOS7 design data and IP management across the semiconductor industry. He has written several articles and white papers on SoC design data management solutions. I have known Karim for more than a dozen years, and he is a friendly, funny, and smart person you will enjoy hearing him speak. Karim has received his Bachelor of Science degree in Computer Science from the University of Texas and holds a patent on defining a universal data management adapter to be used for integration with any EDA tool.

Be sure to sign up using your corporate email address now – here.

 

About ClioSoft Inc.

ClioSoft® is the pioneer and leading developer of enterprise system-on-chip (SoC) design configuration and IP-management solutions for the semiconductor industry. The company provides two unique platforms that enable SoC/IP design-management and reuse.

The SOS7 platform is the only design-management solution for multi-site design collaboration for all types of designs – analog, digital, RF and mixed-signal. The designHUB® platform provides a collaborative IP reuse ecosystem for enterprises.

ClioSoft customers include the top 20 semiconductor companies worldwide. The company is headquartered in Fremont, CA with sales offices and distributors in the United States, United Kingdom, Europe, Israel, India, China, Taiwan, South Korea and Japan. For more information visit www.cliosoft.com