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September 13, 2019September 19, 2019

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am
Categories: ClioSoft, EDA, Events

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. … Read More

November 5, 2018

The Changing Face of IP Management

The Changing Face of IP Management
by Alex Tan on 11-05-2018 at 11:00 am
Categories: ClioSoft, EDA, IP

Aristotle once said “The whole is greater than the sum of its parts”. The notion of synergism echoes the importance of leveraging design IPs to the maximum extent with the rest of the system under development, in order to ensure a successful SoC design outcome in a shorter development cycle.

SoC design cost and entry point
For over… Read More

September 3, 2018

IP Management Using both Git and Methodics

IP Management Using both Git and Methodics
by Daniel Payne on 09-03-2018 at 12:00 pm
Categories: EDA, Methodics

I use Quicken to manage my business and personal finances because it saves me so much time by downloading all of my transactions from Chase for credit card, Amazon for credit card, Wells Fargo for banking and Schwab for IRA. Likewise, for IP management in SoC design you want an app like Quicken that plays well with other tools that you… Read More

March 30, 2018

FlexE at SoC IP Days with Open Silicon

FlexE at SoC IP Days with Open Silicon
by Daniel Nenni on 03-30-2018 at 12:00 pm
Categories: AI, Automotive, Events, FinFET, IoT, IP, Open-Silicon, RISC-V, Security

On Thursday April 5[SUP]th[/SUP] the Design and Reuse SoC IP days continues in Santa Clara at the Hyatt Regency (my favorite hangout). SemiWiki is a co-sponsor and I am Chairman of the IP Security Track. More than 400 people have registered thus far and I expect a big turnout, if you look at the program you will see why. You should also… Read More

July 20, 2017

IP Diligence

IP Diligence
by Bernard Murphy on 07-20-2017 at 12:00 pm
Categories: Consensia, EDA

I hinted earlier that Consensia would introduce at DAC their comprehensive approach to IP management across the enterprise, which they call DelphIP (oracle of Delphi, applied to IP). I talked with Dave Noble, VP BizDev at Consensia to understand where this fits in the design lifecycle.

IP management means a lot of different things.… Read More

April 14, 2017June 14, 2019

IP Traffic Control

IP Traffic Control
by Bernard Murphy on 04-14-2017 at 7:00 am
Categories: Dassault Systemes, EDA

From an engineering point of view, IP is all about functionality, PPA, fitness for use and track record. From a business/management point of view there are other factors, just as critical, that relate less to what the IP is and more to its correct management and business obligations. The problems have different flavors depending… Read More

March 9, 2017June 14, 2019

ClioSoft Crushes it in 2016!

ClioSoft Crushes it in 2016!
by Daniel Nenni on 03-09-2017 at 7:00 am
Categories: ClioSoft, EDA

If you are designing chips in a competitive market with multiple design teams and IP reuse is a high priority then you probably already know about the ClioSoft SOS Platform. What you probably did not know however is how well they are doing with the re-architected version of their integrated design and IP management software.

We have… Read More

February 13, 2017June 14, 2019

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design
by Mitch Heins on 02-13-2017 at 12:00 pm
Categories: ClioSoft, EDA

A couple weeks ago I gave a heads-up about a webinar that was being hosted by ClioSoft, Qorvo and Keysight. The topic of the webinar was how to manage custom RF designs across multiple design teams and CAD flows. The webinar was held on February 1[SUP]st[/SUP] and included presentations by Marcus Ray of Qorvo and Michele Azarian of… Read More

January 23, 2017June 14, 2019

Qorvo and KeySight to Present on Managing Collaboration for Multi-site, Multi-vendor RF Design

Qorvo and KeySight to Present on Managing Collaboration for Multi-site, Multi-vendor RF Design
by Mitch Heins on 01-23-2017 at 12:00 pm
Categories: ClioSoft, EDA, IP

Over the last several weeks I’ve been having a lot of discussions with colleagues around IP reuse and design data management. This led me to a discussion with Ranjit Adhikary, Marketing Vice President for ClioSoft.

ClioSoft is best known for their design collaboration software platform called SOS. They also sell an enterprise… Read More

July 18, 2016June 14, 2019

10 challenges in IP design collaboration

10 challenges in IP design collaboration
by Don Dingee on 07-18-2016 at 4:00 pm
Categories: ClioSoft, EDA

Enterprise design management can be summed up in one word: collaboration. Intellectual property (IP) reuse and the success of distributed system-on-chip (SoC) design efforts depend strongly on how well designers can collaborate. As time-to-market windows have shortened, the challenges around design collaboration have… Read More

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Tag: ip management

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

The Changing Face of IP Management

IP Management Using both Git and Methodics

FlexE at SoC IP Days with Open Silicon

IP Diligence

IP Traffic Control

ClioSoft Crushes it in 2016!

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design

Qorvo and KeySight to Present on Managing Collaboration for Multi-site, Multi-vendor RF Design

10 challenges in IP design collaboration

Upcoming Events

ESSCIRC – ESSDERC 2019

MUGM 2019 – MunEDA User Group...

Webinar: Should I Kill My Formal Run...

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Enabling Verification of Emerging...

Recent Forum Threads

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GLOBALFOUNDRIES Files Patent Infringement Lawsuits

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Semis Price Decay Changes Even War

TSMC 7nm : 28nm Déjà vu all over again?

New Apple iPhones (meh)

World's First Tech Ambassador

Physical Design Engineers @ Apple, Munich, Germany

Graphics Systems Verification Engineer @ Apple, UK

GPU Modelling Engineers @ Apple, UK