WP_Term Object
(
    [term_id] => 8
    [name] => ClioSoft
    [slug] => cliosoft
    [term_group] => 0
    [term_taxonomy_id] => 8
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 102
    [filter] => raw
    [cat_ID] => 8
    [category_count] => 102
    [category_description] => 
    [cat_name] => ClioSoft
    [category_nicename] => cliosoft
    [category_parent] => 157
)
            
WP_Term Object
(
    [term_id] => 8
    [name] => ClioSoft
    [slug] => cliosoft
    [term_group] => 0
    [term_taxonomy_id] => 8
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 102
    [filter] => raw
    [cat_ID] => 8
    [category_count] => 102
    [category_description] => 
    [cat_name] => ClioSoft
    [category_nicename] => cliosoft
    [category_parent] => 157
)

How to Grow with Poise and Grace, a Tale of Scalability from ClioSoft

How to Grow with Poise and Grace, a Tale of Scalability from ClioSoft
by Mike Gianfagna on 06-23-2020 at 10:00 am

ClioSoft published a white paper recently entitled Best Practices are the Foundations of a Startup. The piece discusses the needs and challenges associated with building a scalable infrastructure to support growth.

Before I get into more details on ClioSoft’s white paper, I would offer my own experience on this topic – the need to build a chip company with scale in mind is absolutely critical. I will draw on my experience at eSilicon.  I was one of the first employees at the company, so I had a front-row seat to watch the company’s growth.  And grow we did, from a modest mainstream ASIC suppler to an advanced 2.5D FinFET ASIC supplier, building some of the most complex chips in the world.

There are many parts of this story. I will focus briefly on just one – the compute infrastructure for chip design and tapeout. In the early days, eSilicon operated its own compute farm, first on-site and then at a co-located facility not far from its headquarters in the Bay Area. We owned the computers and managed the whole thing in house. For the types of chips we were doing, this strategy was predictable and effective.

As we began to grow and move from mainstream designs to cutting-edge FinFET and 2.5D designs, it became clear the “owner/operator” model was going to break. The advanced chips we were contemplating required at least 10X more compute resources, often a lot more than that near tapeout. We couldn’t afford to buy all that gear. And even if we could, hiring enough people to manage a facility like that would be daunting.

The company attacked the problem in two parts.  First, we outsourced our data center operation and the management of it to a large service provider who did that kind of thing all the time.  Our un-manageable capital and manpower problem was now a manageable operating expense problem. Later on, we saw the additional benefits of moving to the cloud, so we did that to further manage expense and allow massive on-demand bursts of compute during tapeout. By staying ahead of the need, our infrastructure was able to scale with the company. I’d like to give a shout-out to the long-time CIO at eSilicon who had the foresight to stay ahead of the curve – Naidu Annamaneni.

Back to the ClioSoft white paper. This discussion treats compute infrastructure scalability as well as design methodology scalability.  The reasons to adopt best practices are explained well. The piece also spends some time on the design management aspects of the problem.  This one has multiple dimensions. Storing and managing design data are part of it of course.

The white paper makes a compelling case for getting collaboration tools such as design data management correct at the beginning of a company’s life. The need for simplicity and agility are also addressed. To whet your appetite, here are some of the topics covered:

  • Naming conventions
  • Data storage and backup conventions and processes
  • Design flows and handoffs
  • Design management tools and methodology
  • Issue tracking and other collaboration tools
  • Project and schedule management

You can access the new ClioSoft white paper here. Happy reading.

ClioSoft was launched in 1997 by Srinath Anantharaman as a self-funded company, with the SOS design collaboration platform as its first product. The objective then, was to help manage front end flows for SoC designs.

The SOS platform was later extended to incorporate analog and mixed-signal design flows wherever Cadence Virtuoso® was predominantly used. SOS is currently integrated with tools from Cadence®, Synopsys®, Mentor and Keysight Technologies®. ClioSoft also provides an enterprise IP management platform for design companies to easily create, publish and reuse their design IPs called designHUB.

Today ClioSoft, driven by the experience and innovation of a number of engineers, is the market leader for design data and IP management solutions and the #1 choice for analog and mixed-signal designers.

 

 


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