Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
by Admin on 03-19-2020 at 11:00 am

Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken
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Debunking Myths of HPC, Cloud and Licensing

Debunking Myths of HPC, Cloud and Licensing
by Admin on 03-19-2020 at 11:00 am

March 19, 2020

11:00 AM (EDT)

Venue:
Online

According to a recent survey, 40% of engineers limit the size or amount of detail for every simulation model due to compute capacity and turnaround time constraints. Recognizing this, smaller and mid-sized companies now seek more affordable, accessible and powerful hardware, making

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Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More


#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers

#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers
by Tom Simon on 06-20-2019 at 10:00 am

It was inevitable that EDA applications would meet the cloud. EDA has a long history of creating some of the most daunting compute challenges. This arises from employing current generation chips to design the next generation chips. Despite growing design complexity, many tools have kept pace and even reduced runtimes from generation… Read More


Lip-Bu Keynote at CDNLive 2019

Lip-Bu Keynote at CDNLive 2019
by Bernard Murphy on 04-10-2019 at 7:00 am

Cadence CEO Lip-Bu Tan is always an interesting guy to listen to for his broader technology industry overview and his insight into emerging tech through his Walden International investments. Though we’re usually heads-down in challenging technical problems, it’s good to look up from time to time to check whether what … Read More


ARM Turns up the Heat in Infrastructure

ARM Turns up the Heat in Infrastructure
by Bernard Murphy on 10-18-2018 at 7:00 am

I don’t know if it was just me but I left TechCon 2017 feeling, well, uninspired. Not that they didn’t put on a good show with lots of announcements, but it felt workman-like. From anyone else it would have been a great show, but this is TechCon. I expect to leave with my mind blown in some manner and it wasn’t. I wondered if the SoftBank … Read More


Cloud FPGA Optimal Design Closure, Synthesis, and Timing Using Plunify’s AI Strategies

Cloud FPGA Optimal Design Closure, Synthesis, and Timing Using Plunify’s AI Strategies
by Camille Kokozaki on 09-25-2018 at 12:00 pm

Plunify, powered by machine learning and the cloud, delivers cloud-based solutions and optimization software to enable a better quality of results, higher productivity and better efficiency for design. Plunify is a software company in the Electronic Design Market with a focus on FPGA. It was founded in 2009, has its HQ in Singapore… Read More


The Robots are Coming!

The Robots are Coming!
by Bernard Murphy on 08-30-2018 at 7:00 am

Moshe Sheier, VP Marketing at CEVA, recently got back from MWC Shanghai and commented that robots are clearly trending. He saw hordes of robots from dozens of companies, begging for someone to brand and offer them in any one of many possible applications: in an airport to guide you to a connecting flight, for elder care, in hospitals… Read More


Liberate Trio Embraces ML and Cloud

Liberate Trio Embraces ML and Cloud
by Alex Tan on 07-05-2018 at 12:00 pm

A chain is as strong as its weakest link. This phrase resonates well in Static Timing Analysis (STA) domain, though it is about accuracy rather than durability. As timing signoff step provides the final performance readings of a design, an STA outcome is as good as its underlying components. Aside from the parasitic extraction … Read More


RISC-V Ready (Tools) Set (Security) Go (Build)

RISC-V Ready (Tools) Set (Security) Go (Build)
by Camille Kokozaki on 06-26-2018 at 12:00 pm

The second Bay Area RISC-V Meetup event was held at the DoubleTree Hilton in Burlingame on June 19 with about 150 attendees. This event was hosted by SiFive and started with a networking session. The topics and speakers for the evening were:

  • Commercial Software Tools – Larry Lapides, Imperas
  • Securing RISC-V Processors
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