Increase Your Layout Team’s Productivity with SkillCAD

Increase Your Layout Team’s Productivity with SkillCAD
by Daniel Nenni on 12-08-2020 at 10:00 am

Webinar
Cadence Virtuoso is by far the most popular layout tool for IC design. This is especially true at advanced process nodes. One of the key reasons for this is its built-in extension language, SKILL. SKILL is a powerful tool to add time saving and customized functionality to the Virtuoso layout editor. For analog and custom design the
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Webinar: Increase Layout Team Productivity with SkillCAD

Webinar: Increase Layout Team Productivity with SkillCAD
by Daniel Nenni on 11-16-2020 at 6:00 am

Header Webinar 1

The Cadence Virtuoso Design System has been one of the premier Integrated Circuit design systems for many years and is used by most major semiconductor companies.  While it is powerful and versatile, it is often not optimized for certain complex, repetitive and time-consuming layout design tasks.

The founder and president … Read More


SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers

SkillCAD Layout Automation Suite has Over 120 Commands Backed by 60 Customers
by Tom Simon on 09-29-2020 at 10:00 am

SkillCAD Layout Automation Suite

Cadence Virtuoso is by far the most popular layout tool for IC design. This is especially true at advanced process nodes. In my opinion one of the key reasons for this is its built-in extension language, SKILL. SKILL is a powerful tool to add time saving and customized functionality to the Virtuoso layout editor. For analog and custom… Read More


CEO Interview: Pengwei Qian of SkillCAD

CEO Interview: Pengwei Qian of SkillCAD
by Daniel Nenni on 09-14-2020 at 6:00 am

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Pengwei Qian is the founder and CEO of SkillCAD, a grassroots EDA company that has amassed the most impressive customer list (60+ companies) I have experienced for a company of this size, absolutely.

Pengwei has a Bachelor’s degree in Physics and a Masters in Material Science from Fudan University and a Masters in Electronic Engineering… Read More


WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for… Read More


WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. … Read More


IP Provider Vidatronic Embraces the ClioSoft Design Management Platform

IP Provider Vidatronic Embraces the ClioSoft Design Management Platform
by Randy Smith on 07-31-2019 at 6:00 am

Having worked at several semiconductor intellectual property (SIP) companies, I know how important it is to have a strong design data management platform for tracking the development and distribution of SIP products. Everyone doing semiconductor design should care about design data management. But for an IP company, it is … Read More


System Implementation Connectivity Verification and Analysis, Including Advanced Package Designs

System Implementation Connectivity Verification and Analysis, Including Advanced Package Designs
by Tom Dillinger on 06-08-2017 at 4:00 pm

Regular Semiwiki readers are aware of the rapid emergence of various (multi-die) advanced package technologies, such as: FOWLP (e.g., Amkor’s SWIFT, TSMC’s InFO); 2D die placement on a rigid substrate (e.g., TSMC’s CoWoS); and, 2.5D “stacked die” with vertical vias (e.g., any of the High Bandwidth Memory,… Read More


ClioSoft Crushes it in 2016!

ClioSoft Crushes it in 2016!
by Daniel Nenni on 03-09-2017 at 7:00 am

If you are designing chips in a competitive market with multiple design teams and IP reuse is a high priority then you probably already know about the ClioSoft SOS Platform. What you probably did not know however is how well they are doing with the re-architected version of their integrated design and IP management software.


We have… Read More


CEO Interview: Srinath Anantharaman of ClioSoft

CEO Interview: Srinath Anantharaman of ClioSoft
by Daniel Nenni on 02-20-2017 at 7:00 am

It will soon be 20 years since ClioSoft started its journey of selling design management software for the semiconductor industry. It was a slow start considering that designs were relatively small and only digital front-end designers had begun to realize the importance of version control and design management. With open source… Read More