Electromagnetic (EM) simulations have been performed on die metal structures since the 1990s. Originally, the analysis was restricted to a single device (e.g., a spiral inductor). The number of on-die devices simulated simultaneously grew with the increasing capabilities of the computers performing the computations. This recently culminated with Ansys’ announcement that HFSS was used to solve an entire 5.5 mm x 5.5 mm 5G radio frequency integrated circuit (RFIC) in under 30 hours.
People have been using the gold standard accuracy of HFSS for decades to solve on-die structures. But isn’t HFSS hard to use and only for electromagnetic simulation experts? What about the on-die designer who must be an expert in layout and SPICE simulation? Is it too much to ask the designers to become an expert in another simulator? Design cycles are getting shorter and a die designer can no longer afford to wait in line for electromagnetic extraction from a core dedicated group of EM simulation experts.
To address the needs of circuit designers, Ansys developed RaptorH. Powered by Ansys HFSS, RaptorH integrates the HFSS solver with the established integration of RaptorX with Cadence Virtuoso. This means that die designers can now run their own HFSS simulations from within the familiar Cadence Virtuoso environment without having to learn a new software interface. Furthermore, RaptorH provides many benefits to simulation of on-die structures.
Figure 1. RaptorH shown integrated with Cadence Virtuoso
The first benefit is that RaptorH fulfills all foundry requirements ranging from compliance with techfile encryption standards to the support of advanced layout-dependent effects (LDE) down to 3nm nodes. This has many implications. A user no longer must guess at the proprietary material proprieties and thicknesses of the backend metallization to get accurate models and the foundries no longer need to worry about disclosing their intellectual property. In addition, the LDE modifications to the metal are automatically implemented in the model generation so that a user does not have to read, interpret, and modify the geometry manually. This means the user can accurately simulate the true manufactured device performance.
Figure 2. Image of layout-dependent effects (LDE)
The black shapes on the left of the figure are the as-drawn shapes. The red shapes on the right of the figure shows how the lines are actually manufactured. RaptorH reads the techfiles and automatically applies LDE for the most accurate model possible.
Geometry simplification is also automated in the RaptorH flow. Old workflows for simulating on-die structures with HFSS included creating a reduced layout file of just the die metal which needed to be simulated. It also included filling in slots and holes in large metal planes and simplifying the vias into a structure that is fast and efficient to simulate. RaptorH now automates this work for the user. You now can select which cells of the hierarchy to include and how large a hole that HFSS will automatically fill for you, significantly reducing engineering time spent on model creation.
Figure 3. Full layout shown on the left
The automatically reduced layout is shown on the right. Notice that the active device metallization is not included, and that some inductors (which were intentionally left out) are not included.
Not only does RaptorH read the techfile documentation from foundries and simplify the geometry for you, but it also automatically exports an S-parameter model and creates a Spectre netlist file and symbol. This makes it very easy to use the EM model in circuit simulations to verify circuit performance.
As system complexity increases, it is no longer adequate for the die designer to model the die metal alone as the die is always placed in a package of some kind. Today’s system-on-chip (SoC) designs are typically placed in ball grid array (BGA) packages and the metal on the die couples electromagnetically to the metal on the BGA. RaptorH allows the designer to import parts of the BGA package for co-simulation to derive the true manufactured performance. This eliminates surprises at the end of the design cycle or during product testing.
Because RaptorH uses the distributed memory matrix (DMM) solving technology, part of Ansys HFSS, there is no need to limit the size of the problem to what can fit on the RAM of a single machine. DMM allows engineers to efficiently utilize existing compute infrastructure to solve the most demanding problems. Beyond using DMM to solve large problems, RaptorH can also use multiple cores on each of the machines using high-performance computing (HPC) licensing to get your simulations done fast.
Want to learn more? Check out the Ansys blog at https://www.ansys.com/blogShare this post via: