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Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023
by Daniel Nenni on 06-19-2023 at 10:00 am

As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering the opening keynote for this year’s SAFE Forum on June 28th at 10:15 a.m. in San Jose, California.

Ansys is the world leader in both system and electronic multiphysics simulation and analysis, with a strong reputation in the semiconductor market for the reliability and accuracy of its Ansys RedHawk-SC family of power integrity signoff products. Ajei’s keynote, “The 3Ps of 3D-IC,” draws from the company’s unique market position that encompasses chip, package, and board design. Leading semiconductor product designers have adopted 2.5D and 3D-IC packaging technologies that allow multiple, heterogeneous silicon die to be assembled or stacked in a small form-factor package. This provides huge advantages in performance, cost, and flexibility — but heightens analysis and design challenges, including thermal analysis, electromagnetic coupling, and mechanical stress/warpage. Samsung Foundry has been on the forefront of enabling 3D-IC with manufacturing innovations and design reference flows that include best-of-breed solutions like those offered by Ansys.

Learn how to Clear 3D-IC Hurdles

Ajei will present an executive perspective of the challenges facing multi-die chip and system designers. Ansys is a multibillion-dollar company with a deep technology background in an array of physics, from chip power integrity to thermal integrity, mechanical, fluidics, photonics, electromagnetics, acoustics, and many more. This broad portfolio gives Ansys a unique perspective of how 3D-IC technology is compressing traditional chip, package, and board design into a single, new, interlinked optimization challenge.

Ajei will explain how this new reality creates three sets of hurdles for chip design teams that threaten to slow the broader adoption of 3D-IC technology by the mainstream IC market. In response to these challenges, Ajei will present his “3Ps,”: which suggest a program of thoughtful solutions for how the design community can tackle these obstacles and move 3D-IC design toward widespread adoption.

ansys 3d-ic

One of the 3Ps stands for partnerships, which are key to Ansys’ successful collaboration with Samsung Foundry. It is clear to any experienced observer of the EDA market that the complexity of today’s design challenges have grown beyond the ability of any one company to solve. This is just as true for semiconductor design tools as it is for the semiconductor manufacturing equipment industry.  – No one vendor delivers all the equipment used in a fab, and no one software vendor can meet all design tool requirements. The way forward is to engage deeply with ecosystem initiatives like SAFE and ensure that customers have access to the best-in-class tools for every step of their design process.

Register for the Samsung Foundry Forum and SAFE Forum and join Ansys in fostering industry collaborations and partnerships to improve the capabilities of the semiconductor industry. Visit the Ansys booth at the SAFE exhibit (June 28 @ Signia by Hilton, San Jose, CA) to speak with EDA experts on 3D-IC design techniques and requirements.

Also Read:

WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC design technology

Chiplet Q&A with John Lee of Ansys

Multiphysics Analysis from Chip to System

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