Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments such as high performance computing (HPC), mobile, client computing, and automotive electronics. The compute demand on systems has also been growing at unbelievable rates every couple of years. The tremendous growth in artificial intelligence (AI) driven systems and advances in deep learning neural network models have certainly contributed to this and pulled us into the “SysMoore Era.” And multi-die systems are becoming essential to address the system demands of the SysMoore Era.
Given the above trends, silicon IP is going to play an even more critical role in the future growth of the semiconductor market. Yesterday’s off-the-shelf IP is not going to cut it when it comes to specific PPA requirements of various applications. It is all about differentiated IP for specific applications and processes. In the SysMoore Era, IP development strategy should be driven not only by looking forward to the next node but also looking at vertical market requirements, horizontally (process variants) and backwards as multi-die systems enable the optimization of process technologies.
Last week, Synopsys announced an expanded agreement with Samsung Foundry to develop a broad portfolio of IP to reduce design risk and accelerate silicon success for automotive, mobile, and HPC markets, and multi-die designs as well. I had an opportunity to chat with John Koeter, senior vice president of product management and strategy for IP at Synopsys. My discussion focused on understanding how this agreement is different and the important role the supported market segments and multi-die systems trend played in arriving at an expanded agreement. Following is a synthesis of my discussion, highlighting the salient points.
Proactive Collaboration by Looking at Vertical Market Needs
Synopsys and Samsung Foundry have a long history of collaborating when it comes to IP development. Generally speaking, IP development in the past was driven by specific mutual customer demand. Given the compressed time-to-market demand of the SysMoore Era, customers cannot afford to wait for long development cycles after specific IP requests. IP development needs to start proactively based on anticipating future vertical market. And that is what Synopsys and Samsung Foundry are doing per this expanded agreement. They will analyze market segments and develop the needed IP to holistically address vertical market needs. For example, together they will consider what a next-generation ADAS chip or a next-generation MCU or next generation mobile chip will look like and proactively develop IP to address those needs. IP will also be optimized according to the end application needs. For instance, PCIe IP for the HPC market will be optimized for minimum possible latency whereas PCIe IP for the automotive market will be optimized for reliability over a wider temperature range.
For the automotive market in specific, Synopsys will optimize IP for Samsung’s 8LPU, SF5A and SF4A automotive process nodes to meet stringent Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements. The auto-grade IP for ADAS SoCs will include design failure mode and effect analysis (DFMEA) reports that can save months of development effort for automotive SoC applications.
Anticipating Multi-die Systems Requirements
As monolithic chip implementations give way to multi-die system implementations, it is no longer about just the next advanced process node. A multi-die system could have various dies in different process nodes and still deliver the performance and power requirements at a reduced cost compared to a monolithic implementation. This opens up the opportunity to consider creating advanced IP (say PCIe Gen6) for older process nodes to support I/O chiplets of a multi-die system. Synopsys and Samsung are proactively considering such opportunities and will develop a portfolio of advanced IP on many process nodes as well as collaborating on developing high-speed UCIe IP for chip-to-chip communication.
Agreement Expansion Leading to Increase of IP Footprint
As a result of the above identified IP collaboration strategies, the availability IP for Samsung Foundry processes is going to increase significantly. For customers, that is a significant uptick in terms of access to IP in the age of post-Covid era when clear supply chains are high up on their requirements list. With this agreement, Synopsys IP available or in development for Samsung processes includes logic libraries, embedded memories, TCAMs, GPIOs, eUSB2, USB 2.0/3.0/3.1/4.0, USB-C/DisplayPort, PCI Express 3.0/4.0/5.0/6.0, 112G Ethernet, Multi-Protocol 16G/32G PHYs, UCIe, HDMI 2.1, LPDDR5X/5/4X/4, DDR5/4/3, SD3.0/eMMC 5.1, MIPI C/D PHY, and MIPI M-PHY G4/G5.
Synopsys’ Certified Design Flows Accelerate Time to Silicon Success
A broad portfolio of IP from a single vendor has multiple advantages, in both business and engineering terms. From an engineering perspective, for example, power grid or pin location misalignments when integrating various IP blocks are going to be less likely. Synopsys is also working very closely with Samsung on the EDA side to develop and certify various reference flows which should help accelerate time to silicon success.
To read the full press release, click here. For more information, contact Synopsys.