Global Variation and Its Impact on Time-to-Market for Designs

Global Variation and Its Impact on Time-to-Market for Designs
by umangdoshi on 04-14-2021 at 2:00 pm

Impact of Global Variation on Delay

We have come a long way from the days of limited and manageable characterization databases with fewer views and smaller library sizes. The technologies we are headed towards pushing characterization to its limits with special modeling for variation, aging and reliability all on a single process, voltage and temperature (PVT).… Read More


Certitude: Tool that can help to catch DV Environment Gaps

Certitude: Tool that can help to catch DV Environment Gaps
by eInfochips on 04-13-2021 at 2:00 pm

Certitude 9

Design verification (DV) is still one of the biggest challenges in the ASIC based product world. In last two decades, we have seen many changes in terms of HVLs and methodologies used for design verification. System Verilog is the most popular HVL these days and UVM is the most popular verification methodology.

Even after such an… Read More


How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs

How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs
by gruggles on 04-12-2021 at 2:00 pm

How PCI Express 6.0 Can Enhance Bandwidth Hungry High Performance Computing SoCs

What do genome sequencing, engineering modeling and simulation, and big data analytics have in common? They’re all bandwidth-hungry applications with complex data workloads. High-performance computing (HPC) systems deliver the parallel processing capabilities to generate detailed and valuable insights from these applications.

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How Mentor became Siemens EDA

How Mentor became Siemens EDA
by Daniel Nenni on 04-05-2021 at 6:00 am

Messy dog food

When I started in EDA the big three were Daisy, Mentor and Valid (DMV as we called them). Then came Synopsys in 1986 followed by Cadence, which was a clever merger between ECAD (Dracula DRC) and Solomon Design. Daisy and Valid were pushed aside and then there were, “Three dogs hovering over one bowl of dog food, not a pretty site.”… Read More


Why In-Memory Computing Will Disrupt Your AI SoC Development

Why In-Memory Computing Will Disrupt Your AI SoC Development
by Ron Lowman on 03-22-2021 at 6:00 am

dwtb q121 in memory comp fig1.jpg.imgw .850.x 1

Artificial intelligence (AI) algorithms thirsting for higher performance per watt have driven the development of specific hardware design techniques, including in-memory computing, for system-on-chip (SoC) designs. In-memory computing has predominantly been publicly seen in semiconductor startups looking to disrupt… Read More


Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud

Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud
by Scott Durrant Gary Ruggles on 03-11-2021 at 6:00 am

dwtb q121 in memory comp fig1.jpg.imgw .850.x

IDC has forecasted that over the next five years, the Global Datasphere — the amount of data that’s created, transferred over the network and stored each year — will increase by over 3X to 175 zettabytes (Figure 1). Much of this is driven by the Internet of Things (IoT), video applications (including video streaming,… Read More


USB 3.2 Helps Deliver on Type-C Connector Performance Potential

USB 3.2 Helps Deliver on Type-C Connector Performance Potential
by Tom Simon on 03-08-2021 at 10:00 am

USB 3.2 Lane Usage

Despite sounding like a minor enhancement version for USB, USB 3.2 introduces many important changes for the USB specification. To see where USB has come from and where it is going, it is essential to look at what is found in USB 3.2. The other salient point is that now the Type-C connector has split out from the underlying USB specification… Read More


EDA Tool Support for GAA Process Designs

EDA Tool Support for GAA Process Designs
by Daniel Nenni on 11-23-2020 at 6:00 am

GAA FinFET

With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.

I will talk… Read More


CEO Interview: Andreas Kuehlmann of Tortuga Logic

CEO Interview: Andreas Kuehlmann of Tortuga Logic
by Bernard Murphy on 10-23-2020 at 6:00 am

CEO interview

You may remember Andreas from his time at Synopsys, where he led the new Software Integrity Business Unit. He joined Tortuga Logic a couple of months ago to lead the company. Given his background in software security, I was eager to get a CEO interview. Andreas is a EE with background at IBM in the PowerPC and EDA. He directed Cadence… Read More


Digital Design Technology Symposium!

Digital Design Technology Symposium!
by Daniel Nenni on 10-07-2020 at 6:00 am

Synopsys Digital Design Symposium 2020
Virtual events are coming fast and furious. Even though we are sheltering there is still the need to pick and choose carefully because time really is big money inside the semiconductor design ecosystem, absolutely.

Synopsys virtual events are high on my list for three reasons:

  1. They are very well organized and professionally done
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