EDA Tool Support for GAA Process Designs

EDA Tool Support for GAA Process Designs
by Daniel Nenni on 11-23-2020 at 6:00 am

GAA FinFET

With the announcement of early PDK availability for the 3nm GAA process node, designers are extremely interested in the characteristics of the new “gate-all-around” transistor structure and how it compares to the existing FinFET device.  The GAA transistor has been denoted as a (horizontal) nanowire or nanosheet.

I will talk… Read More


CEO Interview: Andreas Kuehlmann of Tortuga Logic

CEO Interview: Andreas Kuehlmann of Tortuga Logic
by Bernard Murphy on 10-23-2020 at 6:00 am

CEO interview

You may remember Andreas from his time at Synopsys, where he led the new Software Integrity Business Unit. He joined Tortuga Logic a couple of months ago to lead the company. Given his background in software security, I was eager to get a CEO interview. Andreas is a EE with background at IBM in the PowerPC and EDA. He directed Cadence… Read More


Digital Design Technology Symposium!

Digital Design Technology Symposium!
by Daniel Nenni on 10-07-2020 at 6:00 am

Synopsys Digital Design Symposium 2020
Virtual events are coming fast and furious. Even though we are sheltering there is still the need to pick and choose carefully because time really is big money inside the semiconductor design ecosystem, absolutely.

Synopsys virtual events are high on my list for three reasons:

  1. They are very well organized and professionally done
Read More

Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP

Synopsys talks about their DesignWare USB4 PHY at TSMC’s OIP
by Tom Simon on 09-25-2020 at 6:00 am

USB4 operating modes

When USB initially came out it revolutionized how peripherals connect to host systems. We all remember when Apple did away with many separate connections for mouse, keyboard, audio and more with their first computers supporting USB. USB has continued to develop more flexibility and more throughput. In 2015 Apple again introduced… Read More


Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II

Techniques to Reduce Timing Violations using Clock Tree Optimizations in Synopsys IC Compiler II
by eInfochips on 08-27-2020 at 10:00 am

eInfochips clock flow

The semiconductor industry growth is increasing exponentially with high speed circuits, low power design requirements because of updated and new technology like IOT, Networking chips, AI, Robotics etc.

In lower technology nodes the timing closure becomes a major challenge due to the increase in on-chip variation effect and… Read More


ARC Processor Virtual Summit!

ARC Processor Virtual Summit!
by Daniel Nenni on 08-21-2020 at 6:00 am

ARC Processor Virtual Summit 2020

The ARC Processor has a rich history. Originally named the Argonaut RISC Processor, it was designed for the Nintendo Game Systems in the 1990s. Argonaut Technologies Limited later became ARC International. My first intimate exposure to ARC was in 2009 when Virage Logic acquired ARC. A year later Virage was acquired by Synopsys… Read More


DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?

DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?
by Tom Simon on 07-30-2020 at 10:00 am

Which problems are ripe for AIML

Artificial Intelligence (AI) and Machine Learning (ML) are becoming more and more commonplace in our world. We have Siri, Alexa and Google Assistant that understand our voice commands. Vision systems that recognize objects are used for facial recognition, autonomous driving, medical, geographical and many other applications.… Read More


Accelerating High-Performance Computing SoC Designs with Synopsys IP

Accelerating High-Performance Computing SoC Designs with Synopsys IP
by Daniel Nenni on 07-22-2020 at 6:00 am

Synopsys DesignWare IP

Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.

After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief HistoryRead More


Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes

Design Technology Co-Optimization (DTCO) for sub-5nm Process Nodes
by Tom Dillinger on 06-23-2020 at 6:00 am

scaled metal resistance

Summary
Design Technology Co-Optimization (DTCO) analysis was pursued for library cell PPA estimates for gate-all-around (GAA) devices and new metallurgy options.  The cell design and process recommendations are a bit surprising.

Introduction
During the “golden years” of silicon technology evolution that applied Dennard… Read More


Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Webinar: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Mike Gianfagna on 06-16-2020 at 6:00 am

Screen Shot 2020 06 15 at 6.59.34 PM

I had the opportunity to preview an upcoming webinar from Synopsys on SoC Glitch Power – what it is and how to reduce it. There is some eye-opening information in this webinar. Glitch power is a bigger problem than you may think and Synopsys has some excellent strategies to help reduce the problem. The webinar is available via replay… Read More