High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by admin on 08-04-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential
Read More

DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?

DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?
by Tom Simon on 07-30-2020 at 10:00 am

Which problems are ripe for AIML

Artificial Intelligence (AI) and Machine Learning (ML) are becoming more and more commonplace in our world. We have Siri, Alexa and Google Assistant that understand our voice commands. Vision systems that recognize objects are used for facial recognition, autonomous driving, medical, geographical and many other applications.… Read More


System-level Power and Performance Optimization of AI SoC Architectures

System-level Power and Performance Optimization of AI SoC Architectures
by Daniel Nenni on 07-22-2020 at 10:00 am

timkogel320x24020200626152836

The investment into tackling AI hardware acceleration has grown at breakneck speeds, with many vendors starting 2nd, 3rd, or 4th generation designs. Due to the fierce competition and ever-growing application opportunities for AI, machine learning algorithms, and compilers, architectures are evolving rapidly and branching… Read More


Accelerating High-Performance Computing SoC Designs with Synopsys IP

Accelerating High-Performance Computing SoC Designs with Synopsys IP
by Daniel Nenni on 07-22-2020 at 6:00 am

Synopsys DesignWare IP

Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.

After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief HistoryRead More


Pitfalls of IP Power Estimation for AI & Vision SoCs, and How to Avoid Them

Pitfalls of IP Power Estimation for AI & Vision SoCs, and How to Avoid Them
by admin on 07-14-2020 at 10:00 am

Derya320x240
Accurately estimating power for your vision SoC can make the difference between success and a multi-million dollar failure. Estimating power can be fairly straightforward for a RISC processor, but today’s vision SoC designs include neural networks with intense computation requirements making accurate power estimation
Read More

RISC-V Formal Verification for ISA Compliance

RISC-V Formal Verification for ISA Compliance
by Daniel Nenni on 07-07-2020 at 10:00 am

XiaolinChenHeadshotModifiedto320240

RISC-V is an open standard instruction set architecture introduced in 2010. It has experienced exponential growth in recent years, enabling users to design custom processors more quickly and cost effectively to meet today’s demand for more technological innovations in the CPU, GPU, AI, ML spaces.

However, verification of … Read More


In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP

In-System Safety and Reliability for Automotive SoCs using Innovative Memory IP
by admin on 07-01-2020 at 9:00 am

Synopsys Logo

In the emerging era of large scale SoCs comprised from complex IP, typically designed for AI and automotive applications, designers must embrace an innovative approach to overcome numerous safety and reliability challenges. Therefore, the solution must be scalable, robust and Functional Safety (FuSa) aware, in addition … Read More


WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

WEBINAR: High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by Daniel Nenni on 06-30-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates.

Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential… Read More


Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals
by Daniel Nenni on 06-23-2020 at 10:00 am

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required

Read More

WEBINAR: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

WEBINAR: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
by Daniel Nenni on 06-23-2020 at 10:00 am

Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges … Read More