A successful multi-die design begins at the architecture exploration level. However, the architecture challenges are exacerbated for multi-die designs as performance and power need to be optimized across multiple heterogeneous and homogeneous dies. Disaggregating IPs based on workload demands, selecting the… Read More
Wednesday, September 18, 2024 | 10 a.m. PDT
Migrating analog designs across process nodes can be a complex and time-consuming challenge. In this webinar, Credo will share its experience using Synopsys ASO.ai, part of the Synopsys.ai™ EDA suite, to streamline and accelerate the design migration of analog circuits. With its automated
Accellera invited me to attend their #61DAC panel discussion about the new Portable Stimulus Standard (PSS) v3.0, and the formal press release was also just announced. The big idea with PSS is to enable seamless reuse of stimulus across simulation, emulation and post-silicon debug and prototyping.
Tom Fitzpatrick from Siemens… Read More
Now that live events are filling up there are even more live events especially here in Silicon Valley. Synopsys, the #1 full IP provider, will host a processor summit here in Santa Clara next month. Given the popularity of anything RISC-V, I would expect this event to be very well attended so be sure and register in advance.
The networking… Read More
Synopsys Webinar | Thursday, August 22, 2024 | 10:00 – 10:40 a.m. PT
Join us for an exclusive Synopsys Cloud webinar highlighting the benefits of license management automation. Synopsys Cloud offers hassle-free EDA license management for chip design teams whether EDA tools are run on their own compute farms, in a cloud
As AI models’ demand for computational power escalates at an unprecedented rate, the demand for high-speed, efficient, and low-power solutions has never been greater. This Synopsys webinar will explore the latest technologies and industry trends driving the need to bring optical interconnects deeper into the networking
Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More
During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More
Dan is joined by Robert Ruiz, a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas… Read More
As electronic systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these applications must… Read More
