5X Faster Equivalence Checking with Formality ML-driven DPX

5X Faster Equivalence Checking with Formality ML-driven DPX
by Admin on 06-09-2022 at 10:00 am

Synopsys Webinar | Thursday, June 9, 2022 | 10:00 – 11:00 a.m. Pacific

Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation

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Embedded Applications Get a Helping Hand: Extensible Processor Architectures

Embedded Applications Get a Helping Hand: Extensible Processor Architectures
by Admin on 06-07-2022 at 10:00 am

Synopsys Webinar | Tuesday, June 7, 2022 | 10:00 – 11:00 a.m. PDT

Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial

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Very Short Reach (VSR) Connectivity for Optical Modules

Very Short Reach (VSR) Connectivity for Optical Modules
by Kalar Rajendiran on 05-26-2022 at 6:00 am

Synopsys 112G Ethernet PHY IP for VSR

Bandwidth, latency, power and reach are always the key points of focus when it comes to connectivity. As the demand for more data and higher bandwidth connectivity continue, power management is gaining a lot of attention. There is renewed interest in pursuing silicon photonics to address many of these challenges. There are many… Read More


DSP IP for High Performance Sensor Fusion on an Embedded Budget

DSP IP for High Performance Sensor Fusion on an Embedded Budget
by Admin on 05-24-2022 at 10:00 am

Synopsys Webinar | Tuesday, May 24, 2022 | 10:00 – 11:00 a.m. PDT

The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale

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Protecting High-Speed Interfaces in Data Centers with Security IP

Protecting High-Speed Interfaces in Data Centers with Security IP
by Kalar Rajendiran on 05-23-2022 at 6:00 am

SoCs Have Many Interfaces That Require Security

The never ending appetite for higher bandwidths, faster data interfaces and lower latencies are bringing about changes in how data is processed at data centers. The expansion of cloud to the network edge has introduced broad use of artificial intelligence (AI) techniques for extracting meaning from data. Cloud supercomputing… Read More


Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV

Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV
by Admin on 05-18-2022 at 10:00 am

Wednesday, May 18, 2022 | 10:00 – 11:00 a.m. Pacific

AI, Graphics, CPU, and many modern designs have arithmetic intensive blocks that are hard to verify with traditional techniques. Synopsys VC Formal DPV (Datapath Validation) has been the industry’s golden standard to get closure on datapath verification.

In

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An Efficient Method to Perform Functional ECO Using Formality ECO

An Efficient Method to Perform Functional ECO Using Formality ECO
by Daniel Nenni on 05-12-2022 at 10:00 am

Thursday, May 12, 2022 | 10:00 – 11:00 a.m. Pacific

During complex IP development, effort and time taken to perform a functional ECO is very high. It involves analysis and understanding of huge combinational and sequential blocks, and usually runs into multiple iterations if done manually. For example: the physical netlist

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Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%

Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%
by Eric Esteve on 05-05-2022 at 6:00 am

Table IP 2020 2021 1

Design IP Sales reached $5.45B in 2021, or 19.4% YoY after 16% in 2020, on-sync with semiconductor growth of 26.2% in 2021 according to WSTS. IPnest has released the “Design IP Report” in May 2022, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O,… Read More


Rapidly Scale and Reduce Time-to-Market for Your Designs with Synopsys Cloud

Rapidly Scale and Reduce Time-to-Market for Your Designs with Synopsys Cloud
by Admin on 05-05-2022 at 12:00 am

Presented by

Sridhar Panchapakesan, Director, Program Management, Synopsys; Giancarlo DiPasquale, Sr Technical Specialist, Microsoft

About this talk

Cloud has democratized access to increasing compute power by lowering barriers to entry, creating the flexibility to scale elastically, and enabling distributed workloads.
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Bigger, Faster and Better AI: Synopsys NPUs

Bigger, Faster and Better AI: Synopsys NPUs
by Kalar Rajendiran on 05-03-2022 at 10:00 am

ARC NPX6 440 TOPS

AI-based applications are fast advancing with evolving neural network (NN) models, pushing aggressive performance envelopes. Just a few years ago, performance requirements of NN driven applications were at 1 TOPS and less. Current and future applications in the areas of augmented reality (AR), surveillance, high-end smartphones,… Read More