While web browsing I constantly glance for the padlock symbol to indicate that the site is encrypting any of my form data by using the https prefix, which means that an SSL (Secure Sockets Layer) certificate is being used by the web hosting company. I have peace of mind knowing that my credit card information cannot be easily stolen… Read More
Chiplet Interconnect Challenges and Standards
For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s… Read More
Webinar: Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
Increasingly complex automotive systems are driving the need for new and powerful E/E architectures, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation, differentiated software solutions, model-based design (MBD) workflows… Read More
Driving the Future of HPC Through 224G Ethernet IP
The need for speed is a never-ending story when it comes to data communications. Currently there are a number of trends such as cloud computing, artificial intelligence, Internet of Things (IoT), multimedia applications and consumer expectations driving this demand. All of these trends are accelerating the growth in high-performance-computing… Read More
Chiplet Q&A with John Lee of Ansys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
With… Read More
Webinar: Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT
According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free.
In this joint Synopsys webinar with SyoSil,
Webinar: Requirements for Multi-Die System Success
The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design,… Read More
Curvilinear Mask Patterning for Maximizing Lithography Capability
Masks have always been an essential part of the lithography process in the semiconductor industry. With the smallest printed features already being subwavelength for both DUV and EUV cases at the bleeding edge, mask patterns play a more crucial role than ever. Moreover, in the case of EUV lithography, throughput is a concern, … Read More
Chiplet Q&A with Henry Sheng of Synopsys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was the very personable Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys. Henry currently leads engineering for 3DIC, advanced technology and visualization.
Are we… Read More
ASIP Virtual Seminar 2023
Extending RISC Processors into Flexible Accelerators using ASIP Designer
Wednesday, May 24, 2023
5:00 – 7:00 p.m. CEST | 8:00 – 10:00 a.m. PT
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications
The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for … Read More