Webinar: Application-Specific Processors (ASIPs) for Physical AI

Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation.  Different from NPUs for cloud platforms, Physical AI processors can be made application-specific.  By jointly tuning their ISA and memory architecture to the network models required by the application, power consumption and silicon area are drastically reduced.

Synopsys ASIP Designer is the industry-leading tool to explore, design, and optimize application-specific instruction-set processors (ASIPs), including custom NPUs for physical AI.

In this Synopsys webinar, we present the design of “SmarT”, an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory.

Next, we present a multi-core RISC-V based accelerator for hyperdimensional computing, designed with ASIP Designer by TU Munich. It applies near-memory computing (NMC) to minimize power consumption and memory bandwidth. This 5-core chip is the first university-led tape-out in Germany using TSMC 7nm technology.

Learn about:

• Synopsys ASIP Designer, the industry-leading tool to explore, design and optimize application specific processors
• ASIP Design methodologies to address challenges in jointly optimizing the memory architecture and the computational resources for Physical AI architectures
• Two ASIP designs examples with customize memory architectures for Physical AI applications