See Defacto Technologies at DAC 2026

I have had the pleasure of working with Defacto Technologies for the past 10 years on SemiWiki and I am always impressed with their professionalism and ability to quickly address the challenges of complex SoC design.

From my perspective, Defacto’s technology is designed to improve productivity and design quality by enabling the SoC building process much earlier in the flow and making physically-aware SoC design highly automated before synthesis process. Also, Defacto is showing success managing design formats all together in a joint flow, this lowers greatly the complexity during the design process, this was presented recently in a dedicated webinar on how RTL and IP-XACT are managed together. They are also leveraging AI to make the subsystem generation process and other capabilities much simpler and faster.

This year at DAC in Long Beach (booth #1255, July 27–29), Defacto will be showcasing several advances worth a closer look: an AI assistant designed to speed up design tasks even for less experienced engineers, increasingly seamless management of IP-XACT alongside RTL, UPF, and SDC, and new subsystem generation capabilities. A great showcase for anyone tackling SoC integration challenges today.

Background

Defacto Technologies is an innovative chip design software company providing for more than 23 years breakthrough design solutions to enhance Front-end SoC integration, verification and Signoff by covering RTL, UPF, SDC, IP-XACT & LEF/DEF design formats with rich APIs in Tcl, Python and C++.

Defacto’s journey began with an early focus on moving traditional DFT (Design-for-Test) checks earlier into the RTL stage, a first success that, 15 years ago, led the company to pivot toward broader SoC design solutions aimed at helping customers meet aggressive PPA (Power, Performance, Area) requirements cost-effectively.

Since then, Defacto’s SoC Compiler has been proven for most of the major semiconductor companies as a robust design platform capable of handling the largest and most complex SoCs, strengthening Defacto’s reputation as a company that solves real front-end integration bottlenecks rather than just adding incremental tooling.

By adopting Defacto’s SoC Compiler design solutions, major semiconductor companies are continuously moving from traditional and painful front-end SoC design tasks to a fully automated and unified design methodology. The related ROI has been proven for hundreds of projects.

Headquartered in the French Alps with a US branch in California, Defacto has a worldwide presence with a 24/7 support all over the world.

Target Applications

Markets segments such as HPC, artificial intelligence, automotive, mobile, which require leading edge SoCs with greater functionality, higher performance and much lower consumption are benefiting the most of our solution. Meeting time-to-market requirements and lowering the overall cost including design steps is becoming a critical factor of success where we can help.

Challenges Being Addressed

This year, Defacto is reaching a new level of automation in our solution to build SoCs. Complexity of systems keep growing and today everybody is trying to handle it using AI. This is the main challenge they are addressing this year. By adding an AI support to their tool, they enable SoC designers to benefit from SoC Compiler maturity with the power of AI. With that new level of automation, designers will be able to build & generate pre-synthesis complex SoCs and subsystems 100x faster. Even junior designers will be able to accomplish expert-level SoC design tasks.

The second challenge they address this year is how to migrate smoothly and cost effectively to IP-XACT standard.

Target Audience

• Design teams who integrate internal and 3rd party IP cores
• RTL designers
• SoC design Architects
• Design Verification engineers

Booth Information and Meeting Request URL

Booth #1255 – https://defactotech.com/contact

Also Read:

WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

Webinar: Faster Design Spec to Implementation using IP-XACT

SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability