Webinar: Faster Design Spec to Implementation using IP-XACT

As SoC design flows grow increasingly complex, IP-XACT has become a cornerstone standard throughout the entire development lifecycle: from architecture specification to design assembly and verification. Its growing adoption is reflected in the standard’s continuous evolution, from the 2009 release through 2014 and now to the 2022 revision, and whether driven by internal methodology choices or imposed by customers and providers, IP-XACT is now a reality.

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In practice, IP-XACT comes with significant challenges. First, the format is inherently complex: its XML-based structure is not human-readable, objects carry dense interdependencies, and different organizations often develop their own “flavors” of the standard, creating interoperability friction. Second, and more critically, IP-XACT cannot be treated in isolation, it must remain consistent with other design representations such as RTL, SDC, and register specifications, meaning any error or mismatch can silently propagate across the entire design flow. What design teams truly need is a platform that supports all major standard versions, abstracts away this complexity without sacrificing quality, enables smooth and productive IP-XACT manipulation (building, extracting, and editing), and above all guarantees consistency with RTL to ensure a reliable path to implementation.

Defacto Technologies has been offering an EDA tool called SoC Compiler to efficiently support an IP-XACT design flow for RTL design teams to make IP integration much easier. Their webinar on June 24^th covers a range of topics, like: Pitfalls of IP-XACT, an ideal IP-XACT platform, what SoC Compiler can do in your EDA tool flow.

With SoC Compiler your team members can design with either IP-XACT, RTL or both, while keeping the databases always synchronized, eliminating errors.

Webinar attendees will learn how they can check IP-XACT/RTL consistency, generate any missing views, package IPs, insert IPs, connect IPs, generate top-level views, report connectivity, extract and check system level memory map, and even generate documentation. SoC Compiler users can also use APIs to create, query or edit IP-XACT. Even advanced capabilities like TGI protocol are enabled.

There’s even support for the new Tight Generator Interface (TGI).

Last and not least, the Defacto’s AI Assistant is also presented as a way to help in a smooth tool adoption and also to reduce the IP-XACT required level of expertise.

Webinar Details

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When: June 24^th at 10AM – 11AM PDT

In this Webinar we will show how the Defacto’s SoC design solution fully supports IP-XACT design format. As a unique joint platform managing tightly both IP-XACT, RTL along with other design collaterals such as UPF and SDC, Defacto’s SoC Compiler takes SoC design integration and design packaging to the next level.

Who should attend the webinar
• Design teams who integrate internal and 3rd party IP cores
• RTL designers
• SoC design Architects
• Design Verification engineers

Speakers are Chouki Aktouf, CEO and CTO, and Olivier Florent, Technical Expert.

Related Blogs:

• SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability
• WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language
• Defacto at the 2025 Design Automation Conference #62DAC