A Complete Scalable Solution for IP Signoff

A Complete Scalable Solution for IP Signoff
by Pawan Fangaria on 10-20-2014 at 7:00 am

In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must … Read More


A Complete Timing Constraints Solution – Creation to Signoff

A Complete Timing Constraints Solution – Creation to Signoff
by Pawan Fangaria on 09-28-2014 at 10:00 pm

With the unprecedented increase in semiconductor design size and complexity design teams are required to accommodate multiple design constraints such as multiple power domains for low power design, multiple modes of operation, many clocks running, and third party IPs with different SDCs. As a result timing closure has become… Read More


RTL Designers Can Win a GoPro Camera at DAC

RTL Designers Can Win a GoPro Camera at DAC
by Daniel Payne on 04-30-2014 at 10:05 am

DACis just 33 days away and who wouldn’t want a cool GoPro camerato play with? Your manager will certainly want you to first check out what’s new at DAC if your job involves getting to RTL signoff on time and within budget. The creative folks at Atrenta have figured out how to attract us with the offer of winning a GoPro camera,… Read More


Expert Constraint Management Leads to Productivity & Faster Convergence

Expert Constraint Management Leads to Productivity & Faster Convergence
by Pawan Fangaria on 04-12-2014 at 7:30 am

The SoC designs of today are much more complex than ever in terms of number of clocks, IPs, levels of hierarchies, several modes of operations, different types of validations and checks for growing number of constraints at various stages in the design flow. As a semiconductor design evolves through several stages from RTL to layout,… Read More


Start With The End In Mind – For Complete & Fast Success!

Start With The End In Mind – For Complete & Fast Success!
by Pawan Fangaria on 11-07-2013 at 6:00 am

There is always a rush to converge a semiconductor design toward faster closure, amid increasing divergent trends of multiple IPs and high complexities of various functionalities on a single chip. Every design house struggles hard to evolve its customized design flows with several short paths patched up to fix issues, global… Read More


Don’t Shoot Yourself in the Foot With Timing Exceptions

Don’t Shoot Yourself in the Foot With Timing Exceptions
by Paul McLellan on 08-15-2013 at 1:42 pm

Image RemovedTiming exceptions are ways of guiding design tools, primarily synthesis and static timing analysis (STA), but these days also place & route and perhaps other tools. Most paths in a design go from one register to the next register. Both registers are on the same clock, and the design needs to ensure that the signal… Read More


New Book on Design Constraints

New Book on Design Constraints
by Paul McLellan on 07-20-2013 at 10:18 pm

Image RemovedThere is a new book out from Springer. The subtitle is actually a better description that the title. The subtitle is A Practical Guide to Synopsys Design Constraints (SDC) but the title isConstraining Designs for Synthesis and Timing Analysis. The authors are Sridhar Gangadharan of Atrenta in San Jose and Sanjay … Read More


Properly Handing Of Clock Tree Synthesis Specifications

Properly Handing Of Clock Tree Synthesis Specifications
by Randy Smith on 04-28-2013 at 1:00 pm

Given today’s design requirements with respect to low power, there is increasing focus on the contribution to total power made by a design’s clock trees. The design decisions made by the front-end team to achieve high performance without wasting power must be conveyed to back-end team. This hand-off must be accurate… Read More