CHERI webinar banner
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3917
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3917
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

A Complete Scalable Solution for IP Signoff

A Complete Scalable Solution for IP Signoff
by Pawan Fangaria on 10-20-2014 at 7:00 am

In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must be performed objectively and quickly without requiring experts for each type of testing such as power, timing, CDC, DFT, physical congestion etc. The key challenge for SoC designers and integrators has been verifying the IP and ensuring their worthiness of being integrated into SoC. As the IP can vary in size and complexity by large extent and there is a large spectrum of IP suppliers which is continuously growing, the solution must be flexible and adaptable to accommodate specific needs of particular IP and must be scalable to cover the whole spectrum as well as address emerging needs in future.

Although, I knew about Atrenta’sIP Kit being used at TSMCfor soft IP qualification, I didn’t know about the versatility of this comprehensive solution until I attended the webinarpresented by Robert Beanland, Sr. Director, Corporate Marketing at Atrenta.

The IP Kit performs extensive verification provided by SpyGlass platform on an IP (including RTL, library files, constraints in terms of SDC, UPF/CPF etc. and waivers), cleans up SDC, CDC, UPF/CPF etc., applies the supplied waivers on rules and provides a clean IP with dedicated reports of power dissipation (including power domains), fault coverage, SDC coverage, clocks & timing etc. along with handoff (datasheet and dashboard reports) and standard reports including signoff. It provides a complete package of all reports, constraints, waivers, RTL, libraries and SpyGlass Abstract Models. The SpyGlass Abstract Models are smart models which are unique creations by Atrenta; I will talk about this a little later.The quality of an IP can be easily ascertained through these reports.

The use-model is quite simple (although rigorous work is done under the hood) for anyone to be able to do the IP signoff easily. It just needs you to run three commands: 1) ‘aipk_read’ that reads the design and supporting files and does the design setup & check for goals; 2) ‘aipk_run’ that does the design analysis; and 3) ‘aipk_pack’ that packages the design once all the goals have been met successfully. The process can also be tuned to any specific customer’s needs.

An extensive dashboard allows you to define rules for IP quality report such as pass/fail criteria, customized tests, and power and CDC checks etc. as per company requirements. Additionally, IP specs can be defined for how a rule should look, for example stuck-at conditions, false path propagation etc. Details about any particular test in the report or its rule can be navigated as shown above. Similarly the trend lines for any particular failing or passing rules can be seen automatically.

TSMC has put the Atrenta IP Kit through extensive use in qualifying all Soft IP; it has constituted an on-line portal which can be used for any IP to pass through the IP Kit and generate healthy quality matrix for the IP at hand. Any validated IP can be re-validated again against any new configuration for re-use. In several of the IP qualifications at TSMC, various kinds of problems such as index out of range, unconstrained I/O ports, unsynchronized CDC paths, and many more have been observed which were not known to the IP providers or SoC integrators. This helps tremendously by pin pointing the exact problems, thus helping faster resolution of problems and eliminating longer loops later during SoC integration.

Now is the time to talk about the SpyGlass Abstract Models! The IP Kit can also be used to provide an Abstract Model with high capacity and performance for its effective and fast integration into an SoC. The model is enhanced such that issues internal to the IP are minimized and the model is focussed on connectivity and configuration information with respect to SoC integration. At the SoC level, the IP connected together are signed-off producing the dashboard for SoC Signoff.

The hierarchical SoC abstraction flow enables billion+ gate SoC results to be available in a few hours instead of weeks. Specifically, these models offer substantial reduction in memory (5-10x), massive performance improvement (15-50x) and noise reduction to the extent of 10-100x (i.e. number of violations) compared to flat design analysis. The SoC design houses can build a repository of qualified IP by passing all 3[SUP]rd[/SUP] party as well as internal IP through the IP Signoff process provided by the IP Kit. The Smart Abstract Models can be built out of these qualified IP through IP Acceptance (i.e. validating IP assumptions in the SoC context) and used in SoCs.

By the use of fewer and shorter iterations, the design convergence becomes faster which can reduce the design schedule up to 60%. The IP Signoff with standardized rule sets and other processes, seamless integration into SoC flow, and extensibility to adopt new technologies and 3[SUP]rd[/SUP] party tool reports is extremely beneficial for IP suppliers as well as SoC integrators for internal as well as external usage.

What’s more? Atrenta is further strengthening the IP Kit by adding a new verification capability to automatically incorporate large number of assertions in an IP which can be used at SoC level to ascertain whether an issue relates to configuration, connectivity, or the IP itself. This will provide an additional high productivity boost to SoC integration and signoff. Stay tuned to get this new capability!

Atrenta provides a complete RTL platform for IP as well as SoC Signoff, flexible use-model, high impact and low noise methodology along with high quality management reports. You can learn more about this complete offering in detail by attending the recorded on-line webinar here.

This reminds me about my discussion with Piyush Sancheti, VP, Product Marketing at Atrentaearly in this year where we saw an acute need of standardized sign-off process, both at IP as well as SoC level.
Read more on that – RTL Sign-off – At an Edge to become a Standard.

More Articles by Pawan Fangaria…..

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.