Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More
Tag: signoff
CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis
Date: Tuesday, September 20, 2022
Time: 10:00 – 11:00 (CEST)
Electromigration (EM) impacts design reliability, causing failures over time. That is why it’s important to analyze both the power mesh and signal wires to check that the average, rms, or peak currents will not lead to a permanent failure. Learn how the Cadence
A PI Engineer’s Guide to Up-Leveled Signoff Methodology
August 26, 2021
Overview
Power integrity (PI) engineers have been running Cadence®Sigrity™ tools to perform DC, AC, and power-ripple analysis for decades. Sigrity X technology is recognized by the industry as simply the best to ensure that sufficient, efficient, and stable power is delivered to the components in your design.
Redefining ESD signoff (once again) with Pathfinder-SC
Time:
August 31, 2021
11:30 AM EDT / 4:30 PM BST / 9 PM IST
Venue:
Online
About this Webinar
As semiconductors move into the wafer-scale chip and chiplet era, there is increased focus on the power thermal and reliability area. One of the key aspects of reliability is ESD. While this phenomenon is understood at a higher-level, comprehending… Read More
Accelerate Full-Chip Signoff with Massively Parallel Scalability
Overview
Physical design constraints become a lot more complicated in the advanced nodes, leading to the exponential growth of design rules while adding complexity. Decreasing the active device sizes and higher geometry densities results in increased design rule check (DRC) run time, a big metal fill impact on chip functionality,
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
Achieving Design Robustness in Signoff for Advanced Node Digital Designs
I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More
Webinar: High-Capacity Power Signoff Using Big Data
Want to know how NVIDIA signs off on power integrity and reliability on mega-chips? Read on.
PPA over-design has repercussions in increased product cost and potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance resulting in higher power density, but traditional… Read More
The Transistor is the Foundation of TCAD to Signoff
At the most basic level, semiconductor design is all about transistors. Any report on a large microprocessor or mobile application processor is in awe about how many transistors it contains. Moore’s Law is all about the most economic way to manufacture transistors. Each process generation for the last decade and looking ahead… Read More
A Complete Scalable Solution for IP Signoff
In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must … Read More