Title: WEBINAR l System-Level Thermal Signoff from Chips Through to Racks
Date: Wednesday, October 18, 2023
Time: 10:00 AM Eastern Daylight Time
Duration: 45 minutes
Summary
Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and
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Time:
August 31, 2021
11:30 AM EDT / 4:30 PM BST / 9 PM IST
Venue:
Online
As semiconductors move into the wafer-scale chip and chiplet era, there is increased focus on the power thermal and reliability area. One of the key aspects of reliability is ESD. While this phenomenon is understood at a higher-level, comprehending… Read More
Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More
I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More
Want to know how NVIDIA signs off on power integrity and reliability on mega-chips? Read on.
PPA over-design has repercussions in increased product cost and potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance resulting in higher power density, but traditional… Read More
