Redefining ESD signoff (once again) with Pathfinder-SC

Redefining ESD signoff (once again) with Pathfinder-SC
by Admin on 08-31-2021 at 12:00 am

Time:
August 31, 2021
11:30 AM EDT / 4:30 PM BST / 9 PM IST

Venue:
Online

About this Webinar

As semiconductors move into the wafer-scale chip and chiplet era, there is increased focus on the power thermal and reliability area. One of the key aspects of reliability is ESD. While this phenomenon is understood at a higher-level, comprehending… Read More


A PI Engineer’s Guide to Up-Leveled Signoff Methodology

A PI Engineer’s Guide to Up-Leveled Signoff Methodology
by Admin on 08-26-2021 at 12:00 am

August 26, 2021

Overview

Power integrity (PI) engineers have been running Cadence®Sigrity™ tools to perform DC, AC, and power-ripple analysis for decades.  Sigrity X technology is recognized by the industry as simply the best to ensure that sufficient, efficient, and stable power is delivered to the components in your design.  

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Accelerate Full-Chip Signoff with Massively Parallel Scalability

Accelerate Full-Chip Signoff with Massively Parallel Scalability
by Admin on 06-01-2021 at 12:00 am

Overview

Physical design constraints become a lot more complicated in the advanced nodes, leading to the exponential growth of design rules while adding complexity. Decreasing the active device sizes and higher geometry densities results in increased design rule check (DRC) run time, a big metal fill impact on chip functionality,

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Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
by Mike Gianfagna on 03-23-2020 at 6:00 am

FINAL2 Digital FF iSpatial Flow hi res

Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one… Read More


Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Mike Gianfagna on 03-09-2020 at 10:00 am

Synopsys SemiWiki STARRC Webinar 1

I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More


Webinar: High-Capacity Power Signoff Using Big Data

Webinar: High-Capacity Power Signoff Using Big Data
by Bernard Murphy on 11-07-2017 at 7:00 am

Want to know how NVIDIA signs off on power integrity and reliability on mega-chips? Read on.

PPA over-design has repercussions in increased product cost and potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance resulting in higher power density, but traditional… Read More


The Transistor is the Foundation of TCAD to Signoff

The Transistor is the Foundation of TCAD to Signoff
by Paul McLellan on 06-04-2015 at 7:00 am

At the most basic level, semiconductor design is all about transistors. Any report on a large microprocessor or mobile application processor is in awe about how many transistors it contains. Moore’s Law is all about the most economic way to manufacture transistors. Each process generation for the last decade and looking ahead… Read More


A Complete Scalable Solution for IP Signoff

A Complete Scalable Solution for IP Signoff
by Pawan Fangaria on 10-20-2014 at 7:00 am

In an SoC world driven by IP, where an SoC can have hundreds of IP (sourced not only from 3[SUP]rd[/SUP] party but also from internal business units which can have a lot of legacy) integrated together, it has become essential to have a comprehensive and standard method to verify and signoff the IP. Additionally, these checks must … Read More


A Complete Timing Constraints Solution – Creation to Signoff

A Complete Timing Constraints Solution – Creation to Signoff
by Pawan Fangaria on 09-28-2014 at 10:00 pm

With the unprecedented increase in semiconductor design size and complexity design teams are required to accommodate multiple design constraints such as multiple power domains for low power design, multiple modes of operation, many clocks running, and third party IPs with different SDCs. As a result timing closure has become… Read More


Automatic RTL Restructuring: A Need Rather Than Convenience

Automatic RTL Restructuring: A Need Rather Than Convenience
by Pawan Fangaria on 08-22-2014 at 5:00 pm

In the semiconductor design industry, most of the designs are created and optimized at the RTL level, mainly through home grown scripts or manual methods. As there can be several iterations in optimizing the hierarchy for physical implementation, it’s too late to do the hierarchical optimizations after reaching the floor plan… Read More