Yesterday Cadence had an all-day Signoff Summit where they talked about the tools that they have for signoff in advanced nodes. Well, of course, those tools work just fine in non-advanced nodes too, but at 20nm and 16nm there are FinFETs, double patterning, timing impacts from dummy metal fill, a gazillion corners to be analyzed and so on.
The core of Cadence’s signoff environment consists of 3 tools, two of them new and one of them updated. These are:
- Tempus, Cadence’s new timing engine announced in May
- Voltus, Cadence’s new power grid analysis tool announced a couple of weeks ago
- QRC, Cadence’s parasitic extraction tool
These tools are designed to interact, because at these process nodes signoff is increasingly like tuning a steel-drum for a Caribbean band, where every change you make alters every other note on the drum. Every change you make to the power network alters the parasitics and the timing, and adjustments to the timing change the power demands. You just have to cross your fingers and hope that the changes get smaller and smaller and eventually converge.
There is apparently an ancient Haida saying that “everything depends on everything else.” Sounds like the perfect metaphor for advanced node signoff!
The biggest effect is that voltage affects timing, so accurate analysis of the power grid (especially IR drop) is very important. But timing affects the power supply too: as changes are made to the design to meet timing there an knock-on effects incrementally changing voltage and thermal (and temperature affects timing and power dissipation, and not in a good way). And changes to the power net change all the parasitics. This all needs to be integrated with Allegro and Sigrity to take account of package and board effects since major current changes, especially inrush current when powering up domains that were powered down, can cause huge transients that affect the whole on-chip power network and thus the timing and…you get the idea. Everything depends on everything else.
I wrote about Tempus in detail on Semiwiki when it was announced here. It is a static timing analysis (STA) tool that has been designed from the ground up to be massively parallel. Yesterday Ruben Molina of Cadence said that the sweet spot on a single server is to use 8 cores after which you should distribute the design across multiple servers. Note that Tempus doesn’t just do the easy distribution, doing analysis in parallel of different corners, but also can distribute timing analysis of a single large design.
Voltus is pretty much the same message but for power analysis. For over a decade, Cadence’s analysis in this area has been based on the VoltageStorm technology acquired in the Simplex acquisition renamed EPS. However, Voltus is a completely new tool. I don’t know how much code it shares with Tempus but I’m betting quite a bit, based on the fact that it has the same massively parallel value proposition and the two tools are clearly tightly integrated. It is 10X the speed of other solutions on the market and supports designs of up to one billion instances. What does it do:
- IR drop and electromigration analysis and optimization
- Power consumption calculation and analysis
- Analysis of power impact on design closure, from chip to package to PCB
Also during the day were several presentation by actual users of Cadence’s signoff tools: GlobalFoundries, nVidia, TI, Connexant and LSI Logic. In particular, nVidia is one of the lead customers for Voltus and presented some of their experience.
Information on Voltus is here. The Voltus white paper is here.
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