Artificial intelligence (AI) and machine learning (ML) are hot topics. Beyond the impact these technologies are having on the world around us, they are also having impact on the semiconductor and EDA ecosystem. I posted a blog last week that discussed how Cadence views AI/ML, both from a tool and ecosystem perspective. The is one reason why a recent press release from Cadence regarding the new release of their digital full flow caught my attention.
The press release details the features of the new digital full flow release, which further optimizes power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and AI. According to the press release, “the flow features multiple industry-first capabilities including unified placement and physical optimization engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.”
Another key feature of the new release is iSpatial technology, which Cadence defines as follows: “The iSpatial technology integrates the Innovus™ Implementation System’s GigaPlace™ Placement Engine and the GigaOpt™ Optimizer into the Genus™ Synthesis Solution, providing techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database.”
There are many significant capabilities discussed and results presented in the press release. I’d like to focus on the ML capabilities. In my previously mentioned post about Cadence, Paul Cunningham detailed the strategies Cadence uses for ML deployment. One was “ML inside”, where heuristic algorithms improve thanks to ML and another is “ML outside” where tools learn from prior runs in order to improve future results. It’s interesting to watch a strategy be used in an actual product, and it seemed to me this press release was announcing just that regarding AI/ML.
I got a chance to speak with Kam Kittrell, senior product management group director in the Digital & Signoff Group at Cadence about the press release and my hunch about AI/ML strategy implementation. It turns out the “unified placement and physical optimization engines plus machine learning” are primarily an application of “ML inside”, allowing the tool to do a better job predicting things like downstream delays and congestion. There is also an element of “ML outside” here as well since the flow can train with the details of a particular user’s design – things like libraries and delay settings, so the optimization takes on a design-specific focus. Hearing about a comprehensive strategy on AI/ML one week and then seeing it in action the following week is noteworthy.
The press release includes detailed quotes from MediaTek and Samsung executives about how ML is used for real designs and what results are delivered. Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence also comments on the impact the new flow release is having on customers. Another memorable quote came from Kam during my discussion with him. Regarding the importance of PPA optimization, which is an industry-wide focus, Kam pointed out that “millions of dollars are spent on tens of picoseconds”. I felt this comment accurately captured the dramatic numbers that characterize SoC design.
You can learn more about Cadence digital design and signoff capabilities here. You will find lots of good resources, including a discussion of all the steps in the design flow as well as videos and relevant articles.
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