Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software

Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software
by Admin on 12-30-2022 at 11:47 am

Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so they behave as a single device. The new Tessent Multi-die software delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.

Tessent Multi-die

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DFT Moves up to 2.5D and 3D IC

DFT Moves up to 2.5D and 3D IC
by Daniel Payne on 10-06-2022 at 10:00 am

2.5D and 3D chiplets min

The annual ITC event was held the last week of September, and I kept reading all of the news highlights from the EDA vendors, as the time spent on the tester can be a major cost and the value to catching defective chips from reaching production is so critical. Chiplets, 2.5D and 3D IC design have caught the attention of the test world, … Read More


How to perform large-scale and accurate Density Functional Theory (DFT) simulations with QuantumATK

How to perform large-scale and accurate Density Functional Theory (DFT) simulations with QuantumATK
by Admin on 06-08-2022 at 2:52 pm

Join our FREE online event to learn how to perform large-scale, accurate and reliable density functional theory (DFT) simulations with the QuantumATK platform:

– Discover how to perform accurate and reliable large scale DFT simulations – even at the hybrid functional level – with Linear Combination of Atomic Orbital… Read More


Accelerate DFT Simulations with Xcelium Multi-Core Technology

Accelerate DFT Simulations with Xcelium Multi-Core Technology
by Admin on 05-17-2021 at 12:04 pm

Overview

High-performance DFT simulation is key to completing today’s complex systems on chip (SoCs) on schedule. Because most simulators were developed before the multi-core era, they process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in

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Smarter Product Lifecycle Management for Semiconductors

Smarter Product Lifecycle Management for Semiconductors
by Tom Simon on 03-24-2021 at 10:00 am

Lifecycle Management for Silicon

Product Lifecycle Management (PLM) for electronic systems has moved from a passive ‘fire and forget’ approach to one that is intimately involved not only during design, but also throughout the entire life of every unit delivered to the field. Siemens EDA has a white paper titled “Tessent Silicon Lifecycle Solutions” that talks… Read More


Observation Scan Solves ISO 26262 In-System Test Issues

Observation Scan Solves ISO 26262 In-System Test Issues
by Tom Simon on 03-23-2021 at 10:00 am

Observation scan for ISO 26262

Automotive electronic content has been growing at an accelerating pace, along with a shift from infotainment toward mission critical functions such as traction control, safety systems, engine control, autonomous driving, etc. The ISO 26262 automotive electronics safety standard evolved to help ensure that these systems… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Power in Test at RTL Defacto Shows the Way

Power in Test at RTL Defacto Shows the Way
by Bernard Murphy on 10-15-2020 at 6:00 am

scan chains crossing power domainspng

In the early days of Atrenta I met with Ralph Marlett, a distinguished test expert with many years of experience at Zuken and Recal Redac. He talked me into believing we could do meaningful static analysis for DFT-friendliness at RTL. His work with us really opened my eyes to the challenges that test groups face in integrating their… Read More


Getting Physical to Improve Test – White Paper

Getting Physical to Improve Test – White Paper
by Tom Simon on 08-26-2020 at 6:00 am

Calculating Total Critical Area

One of the most significant and oft repeated trends in EDA is the use of information from layout to help drive other parts of the design flow. This has happened with simulation and synthesis among other things. Of course, we think of test as a physical operation, but test pattern generation and sorting have been netlist based operations.… Read More


Novel DFT Approach for Automotive Vision SoCs

Novel DFT Approach for Automotive Vision SoCs
by Tom Simon on 07-16-2020 at 6:00 am

Mentor Tessent IC Design

You may have seen a recent announcement from Mentor, a Siemens business, regarding the use of their Tessent DFT software by Ambarella for automotive applications. The announcement is a good example of how Mentor works with their customers to assure design success. On the surface the announcement comes across as a nice block and… Read More