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Choose the Right ASIC Manufacturing Model for Your Business

REPLAY: GPU-Powered SPICE: The Way Forward for Analog Simulation

REPLAY: Avoiding CDM (Charged Device Model) ESD Failures

REPLAY: eFPGA – "What a great idea! But I have no idea how I’d use it!"

REPLAY: Ensuring System-level Security Through Hardware/Software Security Verification

REPLAY: Fabless: The Transformation of the Semiconductor Industry

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REPLAY: PAVE360: Of SoCs, Digital Twins, and Validating Autonomous Vehicle Behavior

REPLAY: Thermal-induced Reliability Challenges and Solutions for Advanced IC Design
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Seminar: Mentor Forum for Tessent DFT 2019 India

Seminar: Mentor Forum for Tessent DFT 2019 India
by Daniel Payne on 09-17-2019 at 9:00 am

Overview

Test for the Autonomous Age

The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning
Achieving high test quality and

August 15, 2019September 17, 2019

Can a hierarchical Test flow be used on a flat design?

Can a hierarchical Test flow be used on a flat design?
by Tom Simon on 08-15-2019 at 10:00 am
Categories: EDA, Mentor, a Siemens Business

It is pretty common for physical layout to work from a flattened hierarchy for blocks or even full chips, even though the front-end design starts with a hierarchical representation. This was not always the case. Way back when, the physical layout matched the logical hierarchy during the design process. Of course, this led to all… Read More

January 31, 2019

How to be Smart About DFT for AI Chips

How to be Smart About DFT for AI Chips
by Tom Simon on 01-31-2019 at 12:00 pm
Categories: AI, EDA, Mentor, a Siemens Business

We have entered the age of AI specific processors, where specialized silicon is being produced to tackle the compute needs of AI. Whether they use GPUs, embedded programmable logic or specialized CPUs, many AI chips are based on parallel processing. This makes sense because of the parallel nature of AI computing. As a result, in… Read More

August 22, 2018

The Pain of Test Pattern Bring-up for First Silicon Debug

The Pain of Test Pattern Bring-up for First Silicon Debug
by Daniel Payne on 08-22-2018 at 7:00 am
Categories: EDA, Mentor, a Siemens Business
1 Comment

In the semiconductor world we have divided our engineering talent up into many adjacent disciplines and each comes with their own job titles: Design engineers, Verification engineers, DFT engineers, Test engineers. When first silicon becomes available then everyone on the team, and especially management all have a few big … Read More

February 22, 2018

Mentor Tessent MissionMode Provides Runtime DFT for Self-Correcting Automotive ICs

Mentor Tessent MissionMode Provides Runtime DFT for Self-Correcting Automotive ICs
by Mitch Heins on 02-22-2018 at 12:00 pm
Categories: Automotive, EDA, Mentor, a Siemens Business

Image RemovedThe automotive industry continues push the limits on how “smart” we can make our vehicles and from that, it follows as to how smart we can make the electronics in the vehicles. When I think of smart cars (and smart automotive ICs) I typically think of things like advanced driver-assistance systems (ADAS) that use AI … Read More

January 17, 2018

Mentor Tessent Products Ready for Second Edition of ISO 26262 Coming in March 2018

Mentor Tessent Products Ready for Second Edition of ISO 26262 Coming in March 2018
by Mitch Heins on 01-17-2018 at 7:00 am
Categories: Automotive, EDA, Mentor, a Siemens Business

Image RemovedHave you notice how smart your automobile is getting? Watching the first round of NFL playoffs I lost count on the number of TV commercials showing cars weaving through tight construction zones (and Star Wars figures), big trucks parking in incredibly tight spaces, cars avoiding rear-end collisions and pedestrians,… Read More

January 31, 2017June 14, 2019

Finding Transistor-level Defects Inside of Standard Cells

Finding Transistor-level Defects Inside of Standard Cells
by Daniel Payne on 01-31-2017 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

In the earliest days of IC design the engineering work was always done at the transistor-level, and then over time the abstraction level moved upward to gate-level, cell-level, RTL level, IP reuse, and high-level modeling abstractions. The higher levels of abstraction have allowed systems to be integrated into an SoC that can… Read More

December 16, 2016June 14, 2019

Reducing the Cost of SoC Testing

Reducing the Cost of SoC Testing
by Daniel Payne on 12-16-2016 at 12:00 pm
Categories: Automotive, Cadence, EDA

Every year certain technology themes appear, like at ITC this year a big theme was how to reduce the cost of SoC testing. I spoke with Rob Knoth of Cadence by phone to hear more about this cost of test theme. Rob gave me an example of an SoC that takes 27 seconds on a tester, so at $0.04 per second in test costs amounts to $1.08 per part. If you… Read More

November 14, 2016

CEO Interview: Chouki Aktouf of Defacto Technologies

CEO Interview: Chouki Aktouf of Defacto Technologies
by Daniel Nenni on 11-14-2016 at 7:00 am
Categories: Defacto Technologies, EDA

Image RemovedAs a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based… Read More

October 26, 2016June 14, 2019

DFT Approaches for Giga-gate SoC Designs

DFT Approaches for Giga-gate SoC Designs
by Daniel Payne on 10-26-2016 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

In the early days of IC design there were arguments against using any extra transistors or gates for testability purposes, because that would be adding extra silicon area which in turn would drive up the costs of the chip and product. Today we are older and wiser, realizing that there are product pricing benefits to quickly test each… Read More

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