Webinar: Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation

Webinar: Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
by Admin on 11-15-2023 at 1:51 pm

Synopsys Webinar: Tuesday, November 28, 2023 | 10-11 am. PT

System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic

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Upskill Your Smart Soldiers and Conquer the Chip War in Style!

Upskill Your Smart Soldiers and Conquer the Chip War in Style!
by Sivakumar PR on 07-21-2023 at 6:00 am

Maven Silicon Article Figure 1

My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform… Read More


Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers

Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers
by Admin on 06-20-2023 at 4:18 pm

As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.

This webinar covers comprehensive static verification capabilities… Read More


CadenceTECHTALK: What’s New – Enhanced Design Features with Cadence Modus DFT, ATPG, and Diagnostics

CadenceTECHTALK: What’s New – Enhanced Design Features with Cadence Modus DFT, ATPG, and Diagnostics
by Admin on 05-16-2023 at 2:56 pm

Time: 09:00 BST / 10:00 CEST / 11:00 EEST & Israel / 13:30 IST

The latest 22.1 release of the Cadence® Modus DFT Software Solution contains many new and improved features and capabilities. Join us for this CadenceTECHTALK where you will learn all about the new power, performance, and area (PPA) improvements that Cadence Modus

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Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software

Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software
by Admin on 12-30-2022 at 11:47 am

Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so they behave as a single device. The new Tessent Multi-die software delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.

Tessent Multi-die

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DFT Moves up to 2.5D and 3D IC

DFT Moves up to 2.5D and 3D IC
by Daniel Payne on 10-06-2022 at 10:00 am

2.5D and 3D chiplets min

The annual ITC event was held the last week of September, and I kept reading all of the news highlights from the EDA vendors, as the time spent on the tester can be a major cost and the value to catching defective chips from reaching production is so critical. Chiplets, 2.5D and 3D IC design have caught the attention of the test world, … Read More


How to perform large-scale and accurate Density Functional Theory (DFT) simulations with QuantumATK

How to perform large-scale and accurate Density Functional Theory (DFT) simulations with QuantumATK
by Admin on 06-08-2022 at 2:52 pm

Join our FREE online event to learn how to perform large-scale, accurate and reliable density functional theory (DFT) simulations with the QuantumATK platform:

– Discover how to perform accurate and reliable large scale DFT simulations – even at the hybrid functional level – with Linear Combination of Atomic Orbital… Read More


CEO Interview: Sivakumar P R of Maven Silicon

CEO Interview: Sivakumar P R of Maven Silicon
by Daniel Nenni on 06-25-2021 at 6:00 am

CEO Profile Photo

Sivakumar P R is the Founder and CEO of Maven Silicon. He is responsible for the company’s vision, overall strategy, business, and technology. He is also the Founder and CEO of Aceic Design Technologies.

Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering,… Read More


Accelerate DFT Simulations with Xcelium Multi-Core Technology

Accelerate DFT Simulations with Xcelium Multi-Core Technology
by Admin on 05-17-2021 at 12:04 pm

Overview

High-performance DFT simulation is key to completing today’s complex systems on chip (SoCs) on schedule. Because most simulators were developed before the multi-core era, they process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in

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Smarter Product Lifecycle Management for Semiconductors

Smarter Product Lifecycle Management for Semiconductors
by Tom Simon on 03-24-2021 at 10:00 am

Lifecycle Management for Silicon

Product Lifecycle Management (PLM) for electronic systems has moved from a passive ‘fire and forget’ approach to one that is intimately involved not only during design, but also throughout the entire life of every unit delivered to the field. Siemens EDA has a white paper titled “Tessent Silicon Lifecycle Solutions” that talks… Read More