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Getting Physical to Improve Test – White Paper

Getting Physical to Improve Test – White Paper
by Tom Simon on 08-26-2020 at 6:00 am

One of the most significant and oft repeated trends in EDA is the use of information from layout to help drive other parts of the design flow. This has happened with simulation and synthesis among other things. Of course, we think of test as a physical operation, but test pattern generation and sorting have been netlist based operations. However, just as it was instrumental in other domains, physical information has now been shown to greatly assist with test pattern generation and selection.

In a very interesting white paper released by Mentor, a Siemens business, on the topic of Critical Area Based Test Pattern Optimization for High Quality Test, the authors Ron Press and Andreas Glowatz discuss how physical information from the design can help predict which patterns are going to effectively find the most likely faults. Mentor uses what they call Total Critical Area (TCA) to help assess the likelihood of certain faults occurring. With this information patterns can be gauged based on their effectiveness in reducing defects per million (DPM).

ATPG test patterns have the goal of detecting every possible fault in a design. The truth is that while it is possible, it is not practical. So, test teams spend enormous amounts of time trying to decide what patterns to use. The Mentor paper points out that even if you can detect an extremely high percentage of possible faults, the ones you miss might be the most common. To remedy this, they are looking at the geometry associated with potential faults to assign a priority to them. For instance, the likelihood of an interconnect bridge depends on a number of parameters. The diagram below from the paper shows how TCAs are calculated for their example.

Calculating Total Critical Area - test pattern generation and selection
Calculating Total Critical Area

Mentor’s methodology not only looks at interconnect but looks at cell internals and interactions between adjacent cells. The standard cell library is analyzed by Calibre to produce cell aware models for faults. LEF/DEF data is used to add information about potential interconnect faults. All this is combined to produce the User Defined Fault Model (UDFM) which is design specific. With the UDFM, Mentor’s Tessent TestKompress can help produce the optimal test patterns to find the most important faults and reduce DPM.

The white paper does a good job of explaining each of the cell aware defect types that are modeled as cell-internal defects. In addition, they summarize interconnect fault types and inter-cell bridge defects. Taken together these new fault models are referred to as automotive-grade ATPG. This acknowledges the much higher fault detection rates that they make possible. There is also a short section on small delay defects and how they are handled. The paper also explains the command sequence that would be used to load and sort the pattern set to optimize fault detection based on TCAs.

TCA offers an innovative and rational system for weighted test pattern selection and sorting to help achieve the lowest DPM. Mentor continues to innovate in their test products. They have been a leader in the area for a long time and continue to show that they are investing to ensure that their leadership is maintained. The white paper has a comprehensive appendix showing the details of the critical area reporting. The body of the paper goes into more detail than can be covered here. If you are interested in learning more about the application of TCA, the white paper is available for download and reading from the Mentor website.


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